similar to: [LLVMdev] X86RegisterInfo.td

The target description .td files are allowed to change the default allocation order on a register class by overriding the allocation_order_begin() and allocation_order_end() methods on TargetRegisterClass. Previously, this was used all the time to filter out stack and frame pointers and other reserved registers. I was able to remove most of these custom allocation orders in the tree because the

So I thought I'd try to use the documentation on llvm backends to try to create a DLX backend. I think I've got most of the stuff for the .td files done but I've got some problems. * Do I need to represent the PC in my XXXRegisterInfo.td file; the branch instruction effects it but you can directly access it ... I'm thinking not. * In my Instruction subclasses (in

Right. But there are 8 registers on the floating point stack from ST0 to ST7 and I think llvm is only using ST0 to ST6 in some code fragments. Could this be because of the assumption that X86::FP registers run from X86::FP0 to X86:FP6 ? --Aparna On Wed, May 25, 2011 at 2:28 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On May 25, 2011, at 11:09 AM, aparna kotha wrote:

On May 25, 2011, at 12:08 PM, aparna kotha wrote: > Right. But there are 8 registers on the floating point stack from ST0 to ST7 and I think llvm is only using ST0 to ST6 in some code fragments. Could this be because of the assumption that X86::FP registers run from X86::FP0 to X86:FP6 ? Yes. My guess it that the code converting from FP to ST registers sometimes needs the extra stack slot.

Hello, Given a TargetRegisterClass *RC, I was wondering if there is a way to find out what register class it is directly, instead of comparing it against all the &mytarget::Class1, &mytarget::Class2 etc. This goes back to my original intention of having special query functions for a subset of register classes. Suppose I wanted vector register classes (more than one, say 2-elements and

Dear R-Helpers, I'm working with immunoassay data and 5PL logistic model. I wanted to experiment with different forms of weighting and parameter selection, which is not possible in instrument software, so I turned to R. I am using R 2.14.2 under Win7 64bit, and the 'nls' library to fit the model - I started with the same model and weighting type (1/y) as in the instrument to see

Hi All, I have a CentOS5.2 server using a Qlogic QLE220 HBA, connected to Quantum DX30 and M1800 libraries via a Qlogic SANbox 5600 switch. I've installed the latest (v8.02.14) drivers from Qlogic for the HBA The issue I have is I am missing 2 of the 4 SDLT drives provided by the M1800 Library. The DX30 provides 6 drives, which are listed in dmesg and assigned /dev/st0->5. I would

Hi, How to unlist list column value and add column into data frame. Data frame ID ContractDe PassengersDe TrainnerDe 1 list(ConID=c("Zx","78yu"),ConRes = c("98","Tut")) list(PassID

Hi, I have a problem in our 3.0-based backend that I'm not sure how it should be handled. In summary, I don't know if * The regalloc verifier is too picky? * The register allocator is at fault for spilling the full register when only parts of it are defined? * Something else? The architecture I'm compiling for has registers with three disjoint parts: g, h and l. In one function we

2005/7/24, Chris Lattner <sabre at nondot.org>: > Ah, ok. In that case, you want to put all of the registers in one register > file, and not make the constant register allocatable (e.g. see > X86RegisterInfo.td, and note how the register classes include EBP and ESP, > but do not register allocate them (through the definition of > allocation_order_end()). > > -Chris

I used a brazilian UPS from "TS-Shara" which uses the megatec serial protocol and it works perfectly. Now I have another one from the same brand (TS-Shara) and it uses a USB cable. I found the following: T: Bus=01 Lev=01 Prnt=01 Port=01 Cnt=01 Dev#= 3 Spd=1.5 MxCh= 0 D: Ver= 1.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 8 #Cfgs= 1 P: Vendor=0483 ProdID=0035 Rev= 2.00 S:

Thanks, Ralph, this line worked well :) Here it is, my first patch to LLVM :) I've changed all allocation_order_begin() and allocation_order_end() methods to take const MachineFunction &MF as a parameter. I also added const version of MachineFunction::getInfo<Ty>() method. And I changed three static hasFP() functions to take const reference to MachineFunction. While doing this

> > FYI, in my implementation I just marked the intervals introduced by > spills as being special so that they would not be chosen to be spilled > again. Then they just get colored like every other interval. But they can be uncolored like every other interval then, right? When your algorithm finds out during one iteration that it should spill some interval it checks whether this

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

On Tuesday 07 August 2007 05:00, Anton Vayvod wrote: > > Yes, that's true. But I wonder if we shouldn't be smarter about which > > register we pick to color it. In Bill W's implementation, it was > > essentially random. What was your solution to this? > > I allocated spill intervals at the beginning of each iteration so all the > rest intervals (except of

On Sep 3, 2010, at 10:46 AM, Jeff Kunkel wrote: > It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. > > I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I

Hi Aries, Thank you for your reply. I understand that the registers you mentioned should not be used at will. The problem I don't understand is why not make these registers *unallocatable*. Since in X86RegisterInfo.td, only floating point stack registers ST0 to ST7 and status flag registers are defined as not allocatable, while special registers such as ESP/EIP/EBP are defined as *allocatable

On May 25, 2011, at 11:09 AM, aparna kotha wrote: > Hi Guys, > > I was working on some floating point intensive benchmarks and realize that the floating point register allocation in llvm assumes that there are only 7 floating point registers in X86, whereas the hardware has 8. > > Line number > 00266 assert(Reg >= X86::FP0 && Reg <= X86::FP6 &&

Hi Guys, I was working on some floating point intensive benchmarks and realize that the floating point register allocation in llvm assumes that there are only 7 floating point registers in X86, whereas the hardware has 8. Line number 00266 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); of X86FloatingPoint.cpp. Is there any reason for

Hi all I need to control an UPS TSSahara usign NUT in pfsense and it is not working. Can somenone help ? ups.conf user=root [tsshara] driver = megatec_usb port = auto vendorid = 0483 productid = 0035 desc = "No Break TS-Shara" [myups] driver=usbhid-ups port=auto /usr/local/libexec/nut/megatec_usb -u root -a tsshara -DD Network UPS Tools 2.2.2 - Megatec protocol driver 1.5.14