similar to: A9 Scheduler

Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two

Hello everybody, I'm reading the .td files defining the Cortex-A57 processor, which is a subtarget of AArch64 target, and there is something confusing me in the `AArch64SchedA57.td` file. In the top of `AArch64SchedA57.td`, various processor resource are defined, as follows ``` def A57UnitB : ProcResource<1>; // Type B micro-ops def A57UnitI : ProcResource<2>; // Type

Dear Andrew and the Group, I’m trying come up with a SchedMachineModel for the AMD bulldozer http://en.wikipedia.org/wiki/Bulldozer_(microarchitecture). The model is not exist for the same .Please correct me if am i wrong here. I was going through your reference @ https://llvm.org/svn/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td . But I couldn’t model some of the

Hello Andy, I want to use the existing scheduling models to estimate performance on a subtarget. For that, I am looking at the new llvm-mca tool where they only use SchedReadWrite and state that not supporting Instruction Itineraries is a limitation. I have also read that the Instruction Itineraries allow to model certain things which cannot be represented in the SchedReadWrite however, I am

While using the Hodges Lehmann Mean in DescTools (DescTools::HodgesLehmann), I found that it generated incorrect answers (see <https://github.com/AndriSignorell/DescTools/issues/97> https://github.com/AndriSignorell/DescTools/issues/97). The error is driven by the existence of tied values forcing wilcox.test in Base R to switch to an approximate algorithm that returns incorrect results - see

Hello, Here is one question regarding the LLVM TableGen: Which file in the llvm/lib/Target/X86 folder describes how the bits in the EFLAGS register are modified by the x86 instructions? For example, in the "X86InstrInfo.td" file, lines 2134-2135, it says: let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { def CLC : I<0xF8, RawFrm, (outs), (ins), "clc",

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

I'm sure the x86 scheduler models are causing bloat. Every time a single instruction appears on a line by itself like this in a scheduler model: def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; It causes that instruction to be its own group in the generated output. And its replicated for each CPU. We should look into better using regular expressions or taking

[I tweaked the subject, #262824 did not introduce the problem, it is just the version I am first seeing this problem] A quick update - I have added 'Sched<[]>' as a base class for all instructions, and also: let hasNoSchedulingInfo = 1; to all the Pseudos, but while most of the errors have gone, I still get the diagnostic for 'COPY' thus: error : No schedule

Dear All, Attached files is related to the changes made to add the Schedmodel for a AMD bulldozer target, Please note that , the model is incomplete but has some of the valuables features implemented. Request to the group or someone from AMD for the comments on the implementation. Thanks ~umesh On Wed, Nov 13, 2013 at 8:14 PM, Umesh Kalappa <umesh.kalappa0 at gmail.com>wrote: >

From: Andrew Trick [mailto:atrick at apple.com] Sent: 24 January 2014 21:52 To: Daniel Sanders Cc: LLVM Developers Mailing List (llvmdev at cs.uiuc.edu) Subject: Re: New machine model questions On Jan 24, 2014, at 2:21 AM, Daniel Sanders <Daniel.Sanders at imgtec.com<mailto:Daniel.Sanders at imgtec.com>> wrote: Hi Andrew, I seem to be making good progress on the P5600 scheduler

> On Mar 17, 2018, at 4:04 PM, Craig Topper via cfe-dev <cfe-dev at lists.llvm.org> wrote: > > I'm sure the x86 scheduler models are causing bloat. Every time a single instruction appears on a line by itself like this in a scheduler model: > > def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; > > It causes that instruction to be its own

I just knocked ~400k off the size of the x86 scheduler tables by reducing from 5k+ entries to 2k+ entries per cpu. ~Craig On Tue, Mar 20, 2018 at 6:34 PM, Andrew Trick <atrick at apple.com> wrote: > > > On Mar 17, 2018, at 4:04 PM, Craig Topper via cfe-dev < > cfe-dev at lists.llvm.org> wrote: > > I'm sure the x86 scheduler models are causing bloat. Every time

hi, at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below. $ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 .section __TEXT,__text,regular,pure_instructions testl $570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in

I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've created an initial MyTargetSchedule.td def MyTargetModel : SchedMachineModel { // HW can decode 2 instructions per cycle. let IssueWidth = 2; let LoadLatency = 4; let MispredictPenalty = 16; // This flag is set to allow the

> On Mar 26, 2018, at 5:18 AM, Pedro Lopes via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. > > Specifically looking at ARMScheduleA9.td, I can find both

Hi, >From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required

Hi list, Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see

Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2

Thanks for prompt response, Andy This will work for cases when address is not modified. However this doesn’t seem to work for pre/post increment load stores. Consider data to address forwarding: $x0 = ldr x0, [x1] $x0, $x2 = ldr x2, [x0, 16]! The second instruction will have it’s own latency for address modification ($x0 register). So I don’t see how we can use ReadAdr stuff here. May be