similar to: [PATCH] drm/nouveau: Acknowledge DMA_VTX_PROTECTION PGRAPH interrupts

This makes nouveau recognise and report more kinds of PGRAPH errors, as well as prevent GPU lockups resulting from some of them. Lots of guesswork was involved and some part of this is probably incorrect. Some potential-lockuop situations are handled by just resetting a whole PGRAPH subunit, which doesn't sound like a "proper" solution, but seems to work just fine... for now.

This will fix races between generated ctxprogs and interrupt handler. Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/nv50_grctx.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index d105fcd..9f909ab 100644 ---

Building today in git - kernel 2.6.32 (git) + nouveau (git). Failed as nouveau_irq.c doesn't include <linux/ratelimit.h> Added the include to nouveau_irq.c and was able to compile... not sure that's where it ought to go.

- 'joi' on irc pointed out that this triggers a BUG_ON, because kzalloc could sleep. - The irq handler should restore the value NV03_PFIFO_CACHES, but still it's better if this stuff doesn't happen in the middle of fifo create context. I see no reason in spin locking pgraph create context, it isn't activated at that stage. - Move and rename the lock after some discussion with

https://bugs.freedesktop.org/show_bug.cgi?id=102430 Bug ID: 102430 Summary: nv4x - memory problems when starting graphical application - logs included Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium

Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- drivers/gpu/drm/nouveau/core/core/gpuobj.c | 2 +- drivers/gpu/drm/nouveau/core/core/object.c | 8 ++++---- drivers/gpu/drm/nouveau/core/core/option.c | 2 +- .../drm/nouveau/core/engine/copy/fuc/nva3.fuc.h | 4 ++-- .../drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h | 4 ++--

Hello, I''m using kernel 3.1.0 and I have both / and /home as btrfs. I used suspend to ram quite often and never had a problem, but yesterday I''ve suspended to get into a plane and when I resumed my /home was all about input/output errors. Reboot did not help either. My root (/) did not suffer any problems. Today I''ve upgraded btrfs-progs to latest GIT and tried scrub

Found by sparse. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 03d8935..d7ace31 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@

NV10TCL defines the vertex buffer registers both as arrays and as individual named registers. This causes duplicate register definitions and the individual registers are not used either by the DDX or by the Mesa driver. Francisco Jerez said to remove them all. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- renouveau.xml | 49

He Everyone, We found out that till version 3.02 the Yukon nic is supported after it gives code errors, i'm working a lot with ehtherboot via drbl / clonezilla, and together with Steven Shiau we ask you guys if you can arrange that the Yukon can be supported again. Our thanx in advance. Dave & Steven

This patch enlarges the PCI GART aperture to 512 MB. The current 64MB aperture is too small and should be enlarged. The optimal amound may be card/system-dependent, so a more sophisticated approach may be preferable. In particular, if RAMIN is less than 1MB, a 512MB aperture won't fit. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- drivers/gpu/drm/nouveau/nouveau_sgdma.c

Currently the nv30 and nv40 Gallium drivers are very similar, and contain about 5000 lines of essentially duplicate code. I prepared a patchset (which can be found at http://repo.or.cz/w/mesa/mesa-lb.git/shortlog/refs/heads/unification+fixes) which gradually unifies the drivers, one file per the commit. A new "nvfx" directory is created, and unified files are put there one by one.

nouveau_bo_wait will make the GPU channel wait for fence if possible, otherwise falling back to waiting with the CPU using ttm_bo_wait. The nouveau_fence_sync function currently returns -ENOSYS, and is the focus of the next patch. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 68 ++++++++++++++++++++++++++++++-

On a multicore Linux platform I'm running a simple c test program, to evaluate xapian performance, and inspect advantages in multiple indexing. I'm starting two threads, and each thread writes to his database. main th -> indexing thread_1 -> db1 (dispatcher) -> indexing thread_2 -> db2 I use sched_setaffinity to bind each indexing thread to a specific core.

http://bugzilla.mindrot.org/show_bug.cgi?id=1295 Summary: [PATCH] Transparent proxy support on Linux Product: Portable OpenSSH Version: 4.6p1 Platform: Other OS/Version: Linux Status: NEW Severity: enhancement Priority: P2 Component: ssh AssignedTo: bitbucket at mindrot.org ReportedBy:

http://bugs.freedesktop.org/show_bug.cgi?id=25806 Summary: NV40 vertex corruption (kernel BO deletion too early?) Product: Mesa Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau AssignedTo: nouveau at lists.freedesktop.org

Several nvidia-based systems don't support backlight control via the standard ACPI control mechanisms. Instead, it's necessary for the driver to modify the backlight control registers directly. This patch adds support for determining whether the registers appear to be in use, and if so registers a kernel backlight device to control them. The backlight can then be controlled via

ttm_bo_delayed_delete has a race condition, because after we do: kref_put(&nentry->list_kref, ttm_bo_release_list); we are not holding the list lock and not holding any reference to objects, and thus every bo in the list can be removed and freed at this point. However, we then use the next pointer we stored, which is not guaranteed to be valid. This was apparently the cause of some

It seems that Noveau is assuming that once the FIFO pointer is past a command, that command has finished executing, and all the buffers it used are no longer needed. However, this seems to be false at least on G71. In particular, the card may not have even finished reading the input vertex buffers when the pushbuffer "fence" triggers. While Mesa does not reuse the buffer object itself,

This patch fixes two issues in nv40_miptree_layout. First, pt->width0 is used, which is the size of the whole texture, while width, which is the size of the mipmap level, should be used. Second, the current code does not 64-byte align the pitch of swizzled textures. However, on my NV40 this causes a pgraph error regarding the pitch register (and sometimes a system lockup too), which is fixed