similar to: NFS subdirectory on client is out of sync

This one puzzles me a lot: [thba at vink layout]$ nc script/xw_functions.ample NEdit: getcwd() fails: No such file or directory NEdit: getcwd() fails: No such file or directory [thba at vink layout]$ ll script/xw_functions.ample -rw-rw-r-- 1 thba thba 16829 Oct 25 16:59 script/xw_functions.ample [thba at vink layout]$ pwd /home/thba/workarea/colibri/design/ana/layout [thba at vink layout]$

Hi, I am debugging private backend and faced interesting problem: sometimes spill hoisting creates double stores. (some output from -debug-only=regalloc). First hoisting: Checking redundant spills for 0 at 16r in %vreg19 [16r,144B:0)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5) 0 at 16r 1 at 144B-phi 2 at 240B-phi 3 at 296r 4 at 416B-phi 5 at 472r Merged to stack int: SS#0

Here's a patch to wobbly.c to handle edge snapping with multiple outputs... Also, I tweaked the window edge snapping to include dock window types, to support the case where dock windows may be on the inner edges of multiple monitors (and thus currently ignored as struts in the output workarea setup). I personally think we should include these "inner" struts when calculating the

On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis

Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This

Hi Jonas, >Thanks for your answers. > >In one year, I am going to have something like a semester project. >The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the

Quoting flac-dev-request@xiph.org: > Send Flac-dev mailing list submissions to > flac-dev@xiph.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.xiph.org/mailman/listinfo/flac-dev > or, via email, send a message with subject or body 'help' to > flac-dev-request@xiph.org > > You can reach the person managing the list at >

Ladies and Gentlemen, Greeting and Felicitations! We are running FC1 (Samba 3.0.2) and pam_mount 0.9.20. ?The Linux machine is a domain member, which has PDC and file server running NT4. I have setup Samba and winbind such that a user may log in on the Linux machine without having a local account, authentication being handled by PDC and this works successfully. ?If I login as an ordinary

The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm

I am experiencing a problem with scroll when dragging items to my drop area. I tried using the scroll option, looked through other forum disscussions but I have not been able to find a solution. I have a side by side layout where i drag elements from myTable into dropZone. The workArea div has overflow: scroll enabled. My problem is when the list becomes long and I have to scroll down to get to a

Thanks for your answers. In one year, I am going to have something like a semester project. The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL

Hello Axel, I'm an undergraduate student who has been working on a student project implementing a project like this for our Fourth Year Design Symposium (http://eceprojects.uwaterloo.ca ). Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I think that much of this would hold for your students project as well. The project took significantly longer to complete than we

A simulator should be expecting the machine opcodes not macros. LD shouldn't care at all as long as the object format plays well. I would think it would be better to fix the simulator. Jack ________________________________________ From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of llvmdev-request at cs.uiuc.edu [llvmdev-request at cs.uiuc.edu] Sent: Thursday,

Hey, I'm thinking about the addition of the getWorkareaForOutput method, and I'm wondering if it wouldn't make sense to define the workarea as part of the CompOutput struct and set it up as part of (or replacing?) the updateWorkareaForScreen call. Either that or make the call to getWorkareaForOutput redo the extents calculation on the windows within only that output. Which do you

Hello, my name is Axel Reimer and I am new to this mailing list. I subscribed because I was just thinking about how hard it would be to implement a flac-decoder in VHDL (in order to use it on a Xilinx-FPGA). Since I am working at a University in Germany I was thinking of offering this project for students. What do you think. How much time would you suggest for such an implementation (if only

Hello, I previously sent this message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it

Dear All, I now have my Dom0 working nicely running Ubuntu Jaunty. I am now trying to boot Images I had been using without problem under my previous Xen installation (Gentoo). For the Dom0 host kernel I am using the debian package linux-image-2.6.26-2-xen-686_2.6.26-15_i386.deb. The DomU kernel is one I compiled myself a while ago (sometime last year and has always worked on Gentoo and I think

Hi Pavel, > If you are interested in HDLs perhaps you would be interested in Vlang? > I am currently working on Verilog fronted and I am looking for somebody with > VHDL interest to join the Vlang project. I have never heard about the Vlang project but it seems to be an interesting project. I think I could be interested to join this project and do the VHDL front-end. However, there are

Hi all, the CallGraph pass is only available in opt. Is there any substantial reason for that? Or is it only because it seems not to be useful for llc? I want to use it in an backend that is derived from the CBackend. I need the information what functions are called in every other function to build communication struktures between the functions. The backend is generating VHDL from C code.

Dear R users, my search for a possibility to convert a generated model into VHDL to program an FPGA has still no solution. The problem: caret -> training -> model -> model.rds -> model.xml (PMML) --?--> VHDL-Code --?--> FPGA The (simplified) task: A photo detector with 16 channels is measuring the intensity of 16 different wavelength ranges. These data are classified with the