search for: xxxregisterinfo

Hi! I started writing a LLVM backend for a custom architecture. I have some register and instruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class

Hello... I have a very simple and tiny processor. It doesn't support procedule call. Do I still need to add the code about TargetFrameInfo and implement the stack operations in the XXXRegisterInfo.cpp????? Thanx. Dave.

Dear, I have been going through the Targets registered with llvm. As I was looking around, I found an include statement in the file XXXRegisterInfo.h (XXX is any target), #include "llvm/Target/TargetRegisterInfo.h" The question is there is no folder called Target in my llvm directory (file TargetRegistorInfo.h missing ) and still programs compile in the XXX architecture. I want access to TargetRegisterInfo.h. Can someone point me in...

I'm trying to add support for inline assembly and I keep getting this error: <jal> "<inline asm>:1:2: error: invalid instruction" which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail. This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it can't find JAL even though I can clearly see it in both MatchTable0[] and

On Jan 9, 2007, at 10:01 AM, Scott Michel wrote: > I was able to resolve my previous question about dealing with custom > loads/stores, and following Chris' suggestion, the IBM Cell SPU > backend > can generate code for "int main(void) { return 0; }" without crashing > llc. There's a lot of work still to be done... like getting frame > offsets correctly

I was able to resolve my previous question about dealing with custom loads/stores, and following Chris' suggestion, the IBM Cell SPU backend can generate code for "int main(void) { return 0; }" without crashing llc. There's a lot of work still to be done... like getting frame offsets correctly computed and hauling in the raft of intrinsics that the Cell SDK defines. Three quick

...operand OR instruction, but how do I encode an immediate >> w/o a type inference contradiction? >> >> def : Pat<(set R32C:$rDest, R32C:$rSrc), >> (ORIr32 R32C:$rSrc, 0)>; You current cannot specify move patterns in the .td file. You specify them with XXXRegisterInfo::copyRegToReg and XXXInstrInfo::isMoveInstr. See the PPC or Sparc backend for some simple examples. -Chris -- http://nondot.org/sabre/ http://llvm.org/

So I thought I'd try to use the documentation on llvm backends to try to create a DLX backend. I think I've got most of the stuff for the .td files done but I've got some problems. * Do I need to represent the PC in my XXXRegisterInfo.td file; the branch instruction effects it but you can directly access it ... I'm thinking not. * In my Instruction subclasses (in XXXInstrFormats.td) how do I get the register number/immediate values from the "ins" dag? * Whats the SDNode value for the conditional instructions e....

...sing GPRBase >>> reg class for both src and dst (it's a mov MI). I need a class just for GPR >>> also, since some operands can only map to GPR and not GPRBase, so I can't >>> just replace GPR with GPRBase. >>> >>> >>> You need to look at XXXRegisterInfo.td. >>> You should have something like: >>> def GPR : RegisterClass<"ARM", [i32], 32, (add (seque >>> >>> The list between square brackets are the type bound to this register >>> class. >>> You may want to bound i32 (or whatever) on...

...RBase reg class for both src and dst (it's a mov MI). I need a class just >>>> for GPR also, since some operands can only map to GPR and not GPRBase, so I >>>> can't just replace GPR with GPRBase. >>>> >>>> >>>> You need to look at XXXRegisterInfo.td. >>>> You should have something like: >>>> def GPR : RegisterClass<"ARM", [i32], 32, (add (seque >>>> >>>> The list between square brackets are the type bound to this register >>>> class. >>>> You may want to bo...

...both src and dst (it's a mov MI). I need a class just >>>>> for GPR also, since some operands can only map to GPR and not GPRBase, so I >>>>> can't just replace GPR with GPRBase. >>>>> >>>>> >>>>> You need to look at XXXRegisterInfo.td. >>>>> You should have something like: >>>>> def GPR : RegisterClass<"ARM", [i32], 32, (add (seque >>>>> >>>>> The list between square brackets are the type bound to this register >>>>> class. >>>&gt...

...'s a mov MI). I need a class just >>>>>> for GPR also, since some operands can only map to GPR and not GPRBase, so I >>>>>> can't just replace GPR with GPRBase. >>>>>> >>>>>> >>>>>> You need to look at XXXRegisterInfo.td. >>>>>> You should have something like: >>>>>> def GPR : RegisterClass<"ARM", [i32], 32, (add (seque >>>>>> >>>>>> The list between square brackets are the type bound to this register >>>>>> cl...

...need a class just >>>>>>> for GPR also, since some operands can only map to GPR and not GPRBase, so I >>>>>>> can't just replace GPR with GPRBase. >>>>>>> >>>>>>> >>>>>>> You need to look at XXXRegisterInfo.td. >>>>>>> You should have something like: >>>>>>> def GPR : RegisterClass<"ARM", [i32], 32, (add (seque >>>>>>> >>>>>>> The list between square brackets are the type bound to this register >>&gt...

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the