I'm trying to add support for inline assembly and I keep getting this error:
<jal>
"<inline asm>:1:2: error: invalid instruction"
which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail.
This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it
can't find JAL even though I can clearly see it in both MatchTable0[] and
MnemonicTable
The input was
int main ()
{
asm volatile ("JAL");
return 0;
}
If I go to JAL's definition in XXXInstrInfo.td and change its assembly
string from "JAL" to "jal", it works.
How can I keep using uppercase characters? It seems to be a minor setting
somewhere but can't find it.
Thanks.
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Tim Northover via llvm-dev
2019-Mar-14 09:13 UTC
[llvm-dev] inline assembly matching error
On Thu, 14 Mar 2019 at 00:15, Josh Sharp via llvm-dev <llvm-dev at lists.llvm.org> wrote:> How can I keep using uppercase characters? It seems to be a minor setting somewhere but can't find it.It's not a setting, I'm afraid. LLVM can assemble both upper & lower case instructions (as long as you're careful), but the underlying definition has to be in lower-case. The most obvious example of this is lib/MC/MCParser/AsmParser.cpp:2182 (in function parseStatement) where the mnemonic always gets "lower" called on it before it's handed off to the target. Cheers. Tim.
I'd like to know how this enum is generated
MatchClassKind {
InvalidMatchClass = 0,
OptionalMatchClass = 1,
MCK__MINUS_1, // '-1'
MCK_0, // '0'
MCK_1, // '1'
MCK_R0, // 'R0'
MCK_LAST_TOKEN = MCK_R0,
MCK_CRegs, // register class 'CRegs'
MCK_NRegs, // register class 'NRegs'
MCK_ORegs, // register class 'ORegs'
MCK_RA, // register class 'RA'
MCK_SRegs, // register class 'SRegs'
MCK_ZRegs, // register class 'ZRegs'
MCK_CPURegs, // register class 'CPURegs'
MCK_LAST_REGISTER = MCK_CPURegs,
MCK_Imm, // user defined class 'ImmAsmOperand'
NumMatchClassKinds
};
I do not recognize register class RA. I do have a register named RA but it's
not a class.
Here is an excerpt from my XXXRegisterInfo.td with all the reg classes
definitions
def CPURegs : RegisterClass< ...
def CRegs : RegisterClass<...
def ORegs : RegisterClass<...
def NRegs : RegisterClass<...
def ZRegs : RegisterClass<...
def SRegs : RegisterClass<...
Where does MCK_RA come from?
Thanks.
________________________________
From: Tim Northover <t.p.northover at gmail.com>
Sent: Thursday, March 14, 2019 2:13 AM
To: Josh Sharp
Cc: via llvm-dev
Subject: Re: [llvm-dev] inline assembly matching error
On Thu, 14 Mar 2019 at 00:15, Josh Sharp via llvm-dev
<llvm-dev at lists.llvm.org> wrote:> How can I keep using uppercase characters? It seems to be a minor setting
somewhere but can't find it.
It's not a setting, I'm afraid. LLVM can assemble both upper & lower
case instructions (as long as you're careful), but the underlying
definition has to be in lower-case. The most obvious example of this
is lib/MC/MCParser/AsmParser.cpp:2182 (in function parseStatement)
where the mnemonic always gets "lower" called on it before it's
handed
off to the target.
Cheers.
Tim.
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