search for: xxxinstrinfo

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOpera...

I am trying to understand how LLVM does code generation and I have a couple of questions. I am using LLVM 2.6. First, if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, defm SRA : F3_12<"mysra", 0b100111, sra>; Is this correct? When I run llc with option -march=sparc, after I make the modification, it sti...

On Jan 1, 2010, at 12:51 PM, mmms1841 wrote: > I am trying to understand how LLVM does code generation and I have a couple of questions. > I am using LLVM 2.6. > > First, > if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? > Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > Is this correct? Yes. > When I run llc with option -march=sparc,...

Hi all, is it possible to define an instruction as always having a certain register as operand in XXXInstrInfo.td? I know I can do it defining a single-register register class, but I need that register also to be on a broader class for other operations (and it is not possible for a reg to be in several classes AFAIU). Thanks! Carlos

I am using LLVM 2.8 on Ubuntu 10.10. (new to both) I change name of instruction on XXXInstrInfo.td ( Sparc, X86 and XCore). I looked into XXXGenAsmWriter.inc and I have seen the new instruction name. But when I run llc for the three targets it prints out the old instruction name. For example in XCoreInstrInfo.td I change the name of one of the instruction let say "divs" to &quot...

Hi all, I would like to know if XXXInstrInfo.td or other td files should be the right place to specify Src Reg and Dest Reg in one instruction can't be the same. If so, could you give an example on that? Thanks! Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O...

...1, 2010, at 12:51 PM, mmms1841 wrote: > > I am trying to understand how LLVM does code generation and I have a > > couple of questions. I am using LLVM 2.6. > > > > First, > > if I want to change the name of an instruction, all I need to do is to > > modify the XXXInstrInfo.td, right? Using Sparc as an example, if I > > wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would > > write, > > > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > > > Is this correct? > > Yes. IMHO...

...t; syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops node:$val), (fneg node:$val), [{ return N->hasOneUse(); }]>; and then use that in each target instruction patten in XXXInstrInfo.td, such as: def XXX_MUL : XXXInst< (outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), "mul $dst, -$src1, $src2", [(set $dst, (mul (fneg_su GPR32:$src1), GPR32:$src2))]>; but I would like to believe there's a way to do this with a Pattern<> definition instead...

....e. it's not a far call, no LISR instruction needed. If it is a far call, the LISR instruction precedes the CALL. 1) I'm not sure exactly how to transform the global & external target addresses, nor how to take the transformation and match them to my LISR & CALL instructions in my XXXInstrInfo.td TableGen file. I've been looking at how the Mips target has hi/lo relocations to handle 16-bits of an address at a time, but I don't see how the relocations are inserted(?) into the patterns for the JAL/JALR nodes. Does anyone have any advice on the best way to do this, and/or how the...

...from there in roughly this order: + Global variables (gives you guaranteed non-dead values to test everything with and is likely simpler than getting procedure call ABIs correct). + Simple arithmetic to make sure I'm not being completely insane in my design decisions and get an idea of how the XXXInstrInfo.td will work + Stack spills and function prologue/epilogue. + Function calls and arguments. After about the second stage I was implementing wide swathes of the processor's instruction space, to give me the instructions needed to support the more complicated details. > 1.3) Please help me...

...l), [{ return > N->hasOneUse(); }]>; AFAIK, you don't need to verify for hasOneUse() because the instruction selector will do it for you. Also, it's too restrictive if fneg_su is used alone in some other matching rule. > and then use that in each target instruction patten in XXXInstrInfo.td, such as: > > def XXX_MUL : XXXInst< > (outs GPR32:$dst), > (ins GPR32:$src1, GPR32:$src2), > "mul $dst, -$src1, $src2", > [(set $dst, (mul (fneg_su GPR32:$src1), GPR32:$src2))]>; > > but I would like to believe there's a way to do this...

...hether an operation can only take address registers as its input operands, we replace i32 with iPTR if so, and insert reg-reg move operations if necessary. For example, (load reg, addr:i32) means we read at 'addr' to fill 'reg'. Here, we modify it to (load reg, addr:iPTR). 1.3 in XXXInstrInfo.td, we give (load reg, iPTR:$addr) to match pattern. 1.4 and finally we "hope" default register allocator do the proper thing. 2. add an annotation pass before register allocation. 2.1 we treat both integer and pointer as i32, and hence there is just "addRegisterClass(MVT::i32,...

Hi all, llvm newbie here. I'm trying to learn porting with llvm for study purpose. This is my first query on llvm mailing list.I have some idea about GCC. I choose 'rx' as a target to port as it is also available in GCC. I have done some initial changes with llvm source code to register target with llvm. I need to verify these changes. Can anyone please take a chance to verify it.

I am using LLVM 2.8 on Ubuntu 10.10. I change name of instruction on XXXInstrInfo.td ( Sparc, X86 and XCore). I looked into XXXGenAsmWriter.inc and I have seen the new instruction name. But when I run llc for the three targets it prints out the old instruction name. For example for XCore I change “divs” to “sdiv” like def DIVS_l3r : FL3R<"divs", sdiv>;// d...

I am using LLVM 2.8 on Ubuntu 10.10. (new to both) I change name of instruction on XXXInstrInfo.td ( Sparc, X86 and XCore). I looked into XXXGenAsmWriter.inc and I have seen the new instruction name. But when I run llc for the three targets it prints out the old instruction name. For example for XCore I change “divs” to “sdiv” like >From => def DIVS_l3r : FL3R<"divs&qu...

...f the instructions you are interested. See getRawAllocationOrder(), ResolveRegAllocHint() and UpdateRegAllocHint() hooks in TargetRegisterInfo. ARM has good examples on how to implements them. Ivan On 13/07/2012 09:28, 陳韋任 (Wei-Ren Chen) wrote: > Hi all, > > I would like to know if XXXInstrInfo.td or other td files should be > the right place to specify Src Reg and Dest Reg in one instruction can't > be the same. If so, could you give an example on that? > > Thanks! > > Regards, > chenwj >

...on, because the compiler that comes with the processor design suite is really messy (it is CoSy). I want to have a power compiler like llvm. I read the "writing an LLVM compiler backend" and I have define almost all the files, but I have problems with the files for the instructions set. XXXInstrInfo.td is giving a headache, I have not found enough information about all the things I have to define hear. I also tried program by example and see the files for the PIC16, Sparc and MIPS but they are so different as to get a pattern. Do you have any information I can use for define my new backend? I...

...tch_MnemonicFail. This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it can't find JAL even though I can clearly see it in both MatchTable0[] and MnemonicTable The input was int main () { asm volatile ("JAL"); return 0; } If I go to JAL's definition in XXXInstrInfo.td and change its assembly string from "JAL" to "jal", it works. How can I keep using uppercase characters? It seems to be a minor setting somewhere but can't find it. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists....

...der: > > + Global variables (gives you guaranteed non-dead values to test > everything with and is likely simpler than getting procedure call ABIs > correct). > + Simple arithmetic to make sure I'm not being completely insane in my > design decisions and get an idea of how the XXXInstrInfo.td will work > + Stack spills and function prologue/epilogue. > + Function calls and arguments. > > After about the second stage I was implementing wide swathes of the > processor's instruction space, to give me the instructions needed to > support the more complicated details...

On Jan 9, 2007, at 10:01 AM, Scott Michel wrote: > I was able to resolve my previous question about dealing with custom > loads/stores, and following Chris' suggestion, the IBM Cell SPU > backend > can generate code for "int main(void) { return 0; }" without crashing > llc. There's a lot of work still to be done... like getting frame > offsets correctly