Displaying 11 results from an estimated 11 matches for "writealu".
2018 Apr 05
1
A9 Scheduler
Hi,
I am having some trouble understanding the scheduling scheme for the C-A9.
Looking at the ARMScheduleA9.td file I find this line that overrides the
target SchedWrite with processor specific latencies.
def : SchedAlias<WriteALU, A9WriteALU>;
However, in this same file, I find the lines presented below, which are
mapping the SchedReadWrite to, for example, the ANDri instruction.
//
===---------------------------------------------------------------------===//
// Subtarget-specific overrides. Map opcodes to list of Sche...
2019 Jun 25
2
x86 instructions EFLAGS in TableGen
Hello,
Here is one question regarding the LLVM TableGen:
Which file in the llvm/lib/Target/X86 folder describes how the bits in
the EFLAGS register are modified by the x86 instructions? For example,
in the "X86InstrInfo.td" file, lines 2134-2135, it says:
let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
So it says the Defs of CLC is EFLAGS, but actually the CLC instruction
only clears the "CF" flag in the EFLAGS register and has nothing to do
with the other bits of EFLAGS. So w...
2014 Apr 22
2
[LLVMdev] where is F7 opcode for TEST instruction on X86?
...hen testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
// register class is constrained to GR8_NOREX.
let isPseudo = 1 in
def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src,
i8imm:$mask),
"", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>;
} // Defs = [EFLAGS]
def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
"{$src, %al|al, $src}">;
def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
"{$src, %ax|ax, $src}">;
def TEST3...
2015 Oct 15
3
what can cause a "CPU table is not sorted" assertion
...e.td
def MyTargetModel : SchedMachineModel {
// HW can decode 2 instructions per cycle.
let IssueWidth = 2;
let LoadLatency = 4;
let MispredictPenalty = 16;
// This flag is set to allow the scheduler to assign a default model to
// unrecognized opcodes.
let CompleteModel = 0;
}
def WriteALU : SchedWrite;
def WriteBranch : SchedWrite;
let SchedModel = MyTargetModel in {
// SLOT0 can handles everything
def Slot0 : ProcResource<1>;
// SLOT1 can't handles branches
def Slot1 : ProcResource<1>;
// Many micro-ops are capable of issuing on multiple ports.
def SlotAny : Proc...
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
...T2
T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
(ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
"add", "\t$Rdn, $imm8",
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
Sched<[WriteALU]>;
~Craig
On Sun, Apr 14, 2019 at 12:21 PM Jie Zhou <jzhou41 at cs.rochester.edu<mailto:jzhou41 at cs.rochester.edu>> wrote:
Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2.
It has 12 regular registers (R0 - R12), and R8 - R12 are used.
I can generate mov in...
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2.
It has 12 regular registers (R0 - R12), and R8 - R12 are used.
I can generate mov instruction that from/ R8-R12 to/from R0-R6.
From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html
R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot
use them
2020 May 09
2
[llvm-mca] Resource consumption of ProcResGroups
Hi,
I’m trying to work out the behavior of llvm-mca on instructions with ProcResGroups. My current understanding is:
When an instruction requests a port group (e.g., HWPort015) and all of its atomic sub-resources (e.g., HWPort0,HWPort1,HWPort5), HWPort015 is marked as “reserved” and is issued in parallel with HWPort0, HWPort1, and HWPort5, blocking future instructions from reserving HWPort015
2013 Oct 21
1
[LLVMdev] MI scheduler produce badly code with inline function
...d how to define the in-order machine (reservation
tables) in new model.
For example, if target has IF ID EX WB stages
should I do:
let BufferSize=0 in {
def IF: ProcResource<1>; def ID: ProcResource<1>;
def EX: ProcResource<1>; def WB: ProcResource<1>;
}
def : WriteRes<WriteALU, [IF, ID, EX1, WB]> ;
or
define each stage as SchedWrite type and use WriteSequence to define this
sequence?
Thanks,
Kuan-Hsu
2013/10/16 Andrew Trick <atrick at apple.com>
>
> On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote:
>
> Hi Andy, thanks for you...
2013 Oct 16
0
[LLVMdev] MI scheduler produce badly code with inline function
On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote:
> Hi Andy, thanks for your help!!
> The scheduled code by method A is same as B when using the new machine model.
> it's make sense, but there is the another problem, the scheduled code is badly.
>
> load/store instruction always reuse the same register
I filed PR17593 with this information. However, I
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...gt; { let Latency = 0; }
def ZeroIdiom : SchedPredicate<[{
MI->getOpcode() == X86::XORrr &&
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()
}]>;
def WriteXOR : SchedWriteVariant<[
SchedVar<ZeroIdiom, [ZeroIdiomWrite],
SchedVar<NoSchedPred, [WriteALU]
>;
```
Problems with the current design
--------------------------------
A SchedPredicate is essentially a custom block of C++ code used by the
SubtargetEmitter to generate a condition through a boolean expression.
A SchedPredicate sees all the definitions that are "captured" by the...
2013 Oct 16
3
[LLVMdev] MI scheduler produce badly code with inline function
Hi Andy, thanks for your help!!
The scheduled code by method A is same as B when using the new machine
model.
it's make sense, but there is the another problem, the scheduled code is
badly.
load/store instruction always reuse the same register
Source:
#define N 2000000
static double b[N], c[N];
void Scale () {
double scalar = 3.0;
for (int j=0;j<N;j++)
b[j] =