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Forward to llvmdev ---------- 转发的邮件 ---------- 发件人："Chris Lattner" <clattner at apple.com> 日期：2013年10月22日 下午7:33 主题：Re: [lldb-dev] Has Fast register allocation been finished in 3.3 version? 收件人： <wansheg at gmail.com> 抄送： <lldb-dev at cs.uiuc.edu> On Oct 21, 2013, at 7:43 PM, wansheg at gmail.com wrote: When I use llc command with --regalloc=fast , get error In addition, is lli use fast register allocation? You should probably ask about this on the llvmdev mailing list, you'll...

sorry ! I have re-corrected the title. ------------------ 原始邮件 ------------------ 发件人: "Sheng Wang"<wansheg at gmail.com>; 发送时间: 2009年9月4日(星期五) 下午3:23 收件人: "LLVMdev"<LLVMdev at cs.uiuc.edu>; 主题: [LLVMdev] Dose I need to build llvm-gcc front-end from sourceresolve this error? /* mm.cpp */ #include<iostream> using namespace std; struct xx{ int x; int mm()const;...

Hi, I'm new for llvm . when I build the llvm sample project , find the autoconf version 2.5 is required . Is that necessary ? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090903/661de771/attachment.html>

can you give a detail description about the target architecture? ------------------ Original ------------------ From: "XU Xinfeng"<xu.xinfeng at gatech.edu>; Date: 2009年9月15日(星期二) 上午7:34 To: "llvmdev"<llvmdev at cs.uiuc.edu>; Subject: [LLVMdev] Dear LLVM, Dear LLVM, Now, I have to design special complier for my own multicore microprocessor with cusomized

Hi, I'm surporiseing that the loop carried dependence analysis is not exsited ; This problem can't be resolved in the future ?

Hello llvmers: I'm study Fast register allocation in codegen. I get confused with isKill flag in MachineOperand. I thin "isKill" flag the last Use Reference. But, Fast Register doesn't require LiveVariable Analysis which will mark isKill Flag for global virtual Register. So during Fast RegisterAllocation, Faster Register Allocation procedure can't determine

I first install the gcc-4.2.4 . then I set CC and CXX export CC= "path of my gcc-4.2.4" export CXX="path of my g++-4.2.4" after that , I config and make . error occur like this : /home/ws/software/gcc-4-2/bin/gcc -c -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -pedantic -Wno-long-long -Wno-variadic-macros

...tent-Type: text/plain; charset="utf-8" > > Forward to llvmdev > ---------- ????? ---------- > ????"Chris Lattner" <clattner at apple.com> > ???2013?10?22? ??7:33 > ???Re: [lldb-dev] Has Fast register allocation been finished in 3.3 version? > ???? <wansheg at gmail.com> > ??? <lldb-dev at cs.uiuc.edu> > > > On Oct 21, 2013, at 7:43 PM, wansheg at gmail.com wrote: > > > When I use llc command with --regalloc=fast , get error > > In addition, is lli use fast register allocation? > > > You should prob...

/* mm.cpp */ #include<iostream> using namespace std; struct xx{ int x; int mm()const; int mm(); }; int xx::mm() const { return const_cast<xx*>(this)->mm(); } int xx::mm() { cout<<"ok"<<endl; return x; } int main() { xx x; x.mm(); return 0; }

Is there some description module that support for pipeline usage exposing character ? Some DSP has clustered architecture , Is LLVM fitted for the clustered-architecture ?

I'n now finding a good compiler infrastructure for our DSP processor the target DSP architecture that we plan to port have two special character : 1. SIMD instruction is the key of performance a>the SIMD instruction format is simple as mulit register = mulit register opcode multi-register destination src_1 src_2 b> the register

I'm now finding a good compiler infrastructure for our DSP processor the target DSP architecture that we plan to port have two special character : 1. SIMD instruction is the key of performance a>the SIMD instruction format is simple as mulit register = mulit register opcode multi-register destination src_1 src_2 b> the register of

I'm now finding a good compiler infrastructure for our DSP processor the target DSP architecture that we plan to port have three special character : 1. SIMD instruction is the key of performance a>the SIMD instruction format is simple as mulit register = mulit register opcode multi-register destination src_1 src_2 b> the register of

Hello llvmers: I'm study Fast register allocation in codegen. I get confused with isKill flag in MachineOperand. I thin "isKill Because Fast Register doesn't require LiveVariable Analysis , So during Fast RegisterAllocation, the Allocation procedure can't determine if this use reference is the last use ( isKill flag is missed for global Virtual register without

Hello llvmer: I am develop new registerb allocation for my study . my register allocation do not depend on live variable . I add an option which will be cheked whether the pass should be add or not in "addOptimizeRegalloc ,". But live variable analysis still appeare After debug,I'm sure that live variable is not add during addPass stage . FYI ,I disable the phiEliminate,live

Thanks -- View this message in context: http://llvm.1065342.n5.nabble.com/is-liveIns-in-machineBasicBlock-only-valid-for-first-block-in-machine-function-tp63667.html Sent from the LLVM - Dev mailing list archive at Nabble.com.