I'm now finding a good compiler infrastructure for our DSP processor
the target DSP architecture that we plan to port have three special
character :
1. SIMD instruction is the key of performance
a>the SIMD instruction format is simple as
mulit register = mulit register opcode multi-register
destination src_1 src_2
b> the register of destination and source is general register
c> SIMD load /store have no special memory alignment requirement;
2. memory access character that load/store can only access 32bits
memory space each time; In the target architecture, the " char",
"short" , "int" , "float" and "long
long" are all 32bits ( 4bytes) .
this means : for array data[3];
int end = (int ) &data[1] ;
int start = (int) &data[0];
end - start = 1 is true;
3. the clustered-architectue, this means the register file is
distributed into four cluster , In each cluster, private
function-unit connecte to the private register file;
inter-cluster , there is a communicate-bus;
If you are familiar with TigerSharc 201 DSP , you can simple consider
our architecture just as TS201.
Do you think it is easy and possible to port the LLVM to such odd
architecture .
any comment about the probelm that we use LLVM as infrastructure for
the target DSP is appreciated.
Thanks !
