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I am hitting this assertion: assert(I != VRBaseMap.end() && "Node emitted out of order - late"); I am not sure why this assertion is being triggered or what I changed that is causing it. This is asserting when SDValue is FrameIndexSDNode 1. I don't have any code that modified frameindices until my overloaded RegisterI...

...tting the following error from llc, the attachments have llc's debug and the .ll files, respectively. Can anyone shed some light on what I should look at to track this one down? /Users/scottm/play/llvm/branches/llvm-spu/lib/CodeGen/SelectionDAG/ ScheduleDAG.cpp:406: failed assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' -scooter -------------- next part -------------- A non-text attachment was scrubbed... Name: crtbegin.debug Type: application/octet-stream Size: 12231 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/...

...4501a7 in __assert_rtn () #5 0x007c2891 in getPhysicalRegisterRegClass (MRI=0x42010504, VT=4, reg=79) at /Volumes/Gir/devel/llvm/llvm.src/lib/CodeGen/SelectionDAG/ ScheduleDAG.cpp:269 #6 0x007c5218 in llvm::ScheduleDAG::EmitCopyFromReg (this=0x41a25a50, Node=0x41a17f60, ResNo=0, SrcReg=79, VRBaseMap=@0xbfffe218) at /Volumes/Gir/devel/llvm/llvm.src/lib/ CodeGen/SelectionDAG/ScheduleDAG.cpp:304 #7 0x007c5938 in llvm::ScheduleDAG::EmitNode (this=0x41a25a50, Node=0x41a17f60, VRBaseMap=@0xbfffe218) at /Volumes/Gir/devel/llvm/ llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:716 #8 0x007c5f00...

...r from llc, the attachments have llc's > debug and the .ll files, respectively. Can anyone shed some light on > what I should look at to track this one down? > > /Users/scottm/play/llvm/branches/llvm-spu/lib/CodeGen/SelectionDAG/ > ScheduleDAG.cpp:406: failed assertion `I != VRBaseMap.end() && "Node > emitted out of order - late"' > > > -scooter > > <crtbegin.debug> > <testcase.ll> > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc....

...On Behalf Of Bill Wendling Sent: Thursday, January 15, 2009 2:07 PM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Hitting assertion, unsure why On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I am hitting this assertion: > > assert(I != VRBaseMap.end() && "Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices unt...

On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I am hitting this assertion: > > assert(I != VRBaseMap.end() && "Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices unt...

...attachments have llc's >> debug and the .ll files, respectively. Can anyone shed some light on >> what I should look at to track this one down? >> >> /Users/scottm/play/llvm/branches/llvm-spu/lib/CodeGen/SelectionDAG/ >> ScheduleDAG.cpp:406: failed assertion `I != VRBaseMap.end() && "Node >> emitted out of order - late"' >> >> >> -scooter >> >> <crtbegin.debug> >> <testcase.ll> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs...

...ursday, January 15, 2009 2:07 PM > To: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Hitting assertion, unsure why > > On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: >> I am hitting this assertion: >> >> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >> >> I am not sure why this assertion is being triggered or what I changed > that >> is causing it. >> >> This is asserting when SDValue is FrameIndexSDNode 1. >> >> I don't have any co...

...ursday, January 15, 2009 2:07 PM > To: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Hitting assertion, unsure why > > On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: >> I am hitting this assertion: >> >> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >> >> I am not sure why this assertion is being triggered or what I changed > that >> is causing it. >> >> This is asserting when SDValue is FrameIndexSDNode 1. >> >> I don't have any co...

...c's >>> debug and the .ll files, respectively. Can anyone shed some light on >>> what I should look at to track this one down? >>> >>> /Users/scottm/play/llvm/branches/llvm-spu/lib/CodeGen/SelectionDAG/ >>> ScheduleDAG.cpp:406: failed assertion `I != VRBaseMap.end() && "Node >>> emitted out of order - late"' >>> >>> >>> -scooter >>> >>> <crtbegin.debug> >>> <testcase.ll> >>> _______________________________________________ >>> LLVM Developers...

...> To: LLVM Developers Mailing List >> Subject: Re: [LLVMdev] Hitting assertion, unsure why >> >> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah > <Micah.Villmow at amd.com> >> wrote: >>> I am hitting this assertion: >>> >>> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >>> >>> I am not sure why this assertion is being triggered or what I changed >> that >>> is causing it. >>> >>> This is asserting when SDValue is FrameIndexSDNode 1. >>> >...

...> To: LLVM Developers Mailing List >> Subject: Re: [LLVMdev] Hitting assertion, unsure why >> >> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah > <Micah.Villmow at amd.com> >> wrote: >>> I am hitting this assertion: >>> >>> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >>> >>> I am not sure why this assertion is being triggered or what I changed >> that >>> is causing it. >>> >>> This is asserting when SDValue is FrameIndexSDNode 1. >>> >...

On Aug 27, 2010, at 11:53 AMPDT, Yuri wrote: > On 08/27/2010 11:32, Yuri wrote: >> As I understand only one of TCRETURNri64 and RET should be created. >> I have sources of rev.112200. >> >> Here is the stack when TCRETURNri64 instruction is created: >> #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr >> (this=0x30eb000, TID=@0x803a78940,

...odeGen/MachineFunction.cpp:153 #2 0x00000008028ea302 in llvm::BuildMI (MF=@0x30eb000, DL={LineCol = 0, ScopeIdx = 0}, TID=@0x803a9f840) at MachineInstrBuilder.h:147 #3 0x0000000803164513 in llvm::InstrEmitter::EmitMachineNode (this=0x7fffffff7f80, Node=0x4b6c510, IsClone=false, IsCloned=false, VRBaseMap=@0x7fffffff8050) at /tmp/llvm-svn/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:671 #4 0x00000008031f6bdf in llvm::InstrEmitter::EmitNode (this=0x7fffffff7f80, Node=0x4b6c510, IsClone=false, IsCloned=false, VRBaseMap=@0x7fffffff8050) at InstrEmitter.h:118 #5 0x00000008031f5781 in llvm::Schedu...

...List >>> Subject: Re: [LLVMdev] Hitting assertion, unsure why >>> >>> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah >> <Micah.Villmow at amd.com> >>> wrote: >>>> I am hitting this assertion: >>>> >>>> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >>>> >>>> I am not sure why this assertion is being triggered or what I > changed >>> that >>>> is causing it. >>>> >>>> This is asserting when SDValue is FrameInd...

...itter::AddRegisterOperand(MachineInstrBuilder &MIB, > SDValue Op, > unsigned IIOpNum, > const MCInstrDesc *II, > DenseMap<SDValue, unsigned> &VRBaseMap, > bool IsDebug, bool IsClone, bool IsCloned) { > //llvm::errs() << "Op = "; > //Op.dump(); > assert(Op.getValueType() != MVT::Other && > Op.getValueType() != MVT::Glue && > "Chain and gl...

...erOperand(MachineInstrBuilder &MIB, >> SDValue Op, >> unsigned IIOpNum, >> const MCInstrDesc *II, >> DenseMap<SDValue, unsigned> &VRBaseMap, >> bool IsDebug, bool IsClone, bool >> IsCloned) { >> //llvm::errs() << "Op = "; >> //Op.dump(); >> assert(Op.getValueType() != MVT::Other && >> Op.getValueType() != MVT::Glue && &gt...

...ect that has to be implemented with a diamond CFG by the scheduler. The high level ScheduleDAGSDNodes::EmitSchedule does this: for (unsigned i = 0, e = Sequence.size(); i != e; i++) { [...] Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap); [...] } TheInstrEmitter::EmitMachineNode does this: if (II.usesCustomInsertionHook()) { // Insert this instruction into the basic block using a target // specific inserter which may returns a new basic block. bool AtEnd = InsertPos == MBB->end(); MachineBasicBlock *Ne...

...8c80, 0x10015679180, 0x10015671d80 [ORD=50] [ID=0] which then asserts: llvm-trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:292: unsigned int llvm::InstrEmitter::getVR(llvm::SDValue, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue> >&): Assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' failed. What's gone wrong here? Is the order in the SU wrong, or should the scheduler invert the order for scheduling, or something else? Thanks again, Hal -- Hal Finkel Assistant Computational Scientist Leadership Computing...

On 08/27/2010 11:32, Yuri wrote: > As I understand only one of TCRETURNri64 and RET should be created. > I have sources of rev.112200. > > Here is the stack when TCRETURNri64 instruction is created: > #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr > (this=0x30eb000, TID=@0x803a78940, DL={LineCol = 0, ScopeIdx = 0}, > NoImp=false) at