search for: v2i16

...tream vector ISA to make progress on this. Thank you >From your description it seems like you are seeing an incorrect behavior. If that's the case, it should definitely be fixed. Could you provide the complete DAG before and after the erroneous transformation? -Krzysztof Combining: t25: v2i16 = BUILD_VECTOR t27, t22 Before reduceBuildVecToShuffle SelectionDAG has 14 nodes: t0: ch = EntryToken t2: v4i16,ch = CopyFromReg t0, Register:v4i16 %0 // [a b c d] t26: v2i16 = extract_subvector t2, Constant:i32<0> // [a b] t27: i16 = extract_vector_elt t26, Constant:i...

Type::canLoslesslyBitCastTo(Type *Ty) in lib/VMCore/Type.cpp always returns false when it checks whether an integer can be bitcast to a vector or vice versa. For example, (i32 => v2i16) or (v2i16 => i32) is false. But it seems that it returns true if it is checking conversion between two vector types which have the same size. For example, (v4i8 => v2i16) would return true. What is the rationale behind this? -------------- next part -------------- An HTML attachment was s...

...32). This can also be used for > // int-to-int or fp-to-fp conversions, but that is a noop, deleted by > // getNode(). > > If I can assume the bitcast instruction in LLVM IR has the same definition, does > this mean that the following instruction > > %dst = bitcast i32 %src to v2i16 > > is equivalent to the following sequence of instructions (which I think is lossless)? > > store i32 %src, i32* %ptr > %ptr2 = bitcast i32* %ptr to v2i16* > %dst = load v2i16* %ptr2 while there has been some discussion about changing the definition of bitcast, yes, this is curr...

...e bit size (e.g. f32 <-> i32). This can also be used for // int-to-int or fp-to-fp conversions, but that is a noop, deleted by // getNode(). If I can assume the bitcast instruction in LLVM IR has the same definition, does this mean that the following instruction %dst = bitcast i32 %src to v2i16 is equivalent to the following sequence of instructions (which I think is lossless)? store i32 %src, i32* %ptr %ptr2 = bitcast i32* %ptr to v2i16* %dst = load v2i16* %ptr2 I am trying to change all vector types (v2i16 and v4i8) in include/llvm/IntrinsicsMips.td to i32, but I can't do that b...

...; // int-to-int or fp-to-fp conversions, but that is a noop, deleted by > > // getNode(). > > > > If I can assume the bitcast instruction in LLVM IR has the same > definition, does > > this mean that the following instruction > > > > %dst = bitcast i32 %src to v2i16 > > > > is equivalent to the following sequence of instructions (which I think > is lossless)? > > > > store i32 %src, i32* %ptr > > %ptr2 = bitcast i32* %ptr to v2i16* > > %dst = load v2i16* %ptr2 > > while there has been some discussion about changing...

Hi, I was wondering if there is a way to specify macros to help shorten rewriting patterns like these: def : Pat <(v4i8 (mul (v4i8 IntRegs:$a), (v4i8 IntRegs:$b))), (v4i8 (VTRUNEHB (v4i16 (VTRUNEWH (v2i32 (VMPYH (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), subreg_hireg)), (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), subreg_hireg)))), (v2i32 (VMPYH (v2i16 (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), subreg_loreg)), (...

I was trying to do a pattern matching for a rd+imm instruction in my own backend. It looks something like: def: Pat<build_vector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR: $src1,16), GPR:$src2>; OR takes two i32 in registers and SLLI takes one i32 in registers and an immediate. But the immediate '16' does not work here and I tried different ways. May I know if any of you have any idea how to bake an immediate value (16)...

...; I was wondering if there is a way to specify macros to help shorten > rewriting patterns like these: > > def : Pat <(v4i8 (mul (v4i8 IntRegs:$a), (v4i8 IntRegs:$b))), > (v4i8 > (VTRUNEHB > (v4i16 > (VTRUNEWH > (v2i32 > (VMPYH > (v2i16 > (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$a))), > subreg_hireg)), > (v2i16 > (EXTRACT_SUBREG (v4i16 (VSXTBH (v4i8 IntRegs:$b))), > subreg_hireg)))), > (v2i32 > (VMPYH > (v2i16 > (EXTRACT_SUBREG (v4i16 (VSXTBH (...

...), >> (ncmul >> (sext (i16 (extractelt RARegs:$a, imm))), >> (sext (i16 (extractelt RARegs:$b, imm))) >> ) >> ))), >> imm) ) >> >> where RARegs is a register class of type [i32, v2i16]. I want to match >> that pattern in order to have one instruction which takes 2 vectors >> (complex numbers) and gives me another vector. Unfortunately, I am >> running into multiple tblgen type inference exceptions. I am new to llvm >> codegen. >> >> First of a...

Hi, How can we set the minimum addressable memory unit to be 32 bit ? As far as I know, getTargetData() provides all type sizes and alignments to compute address offsets assuming a MAU of 8 bits. But what if I have a MAU of 32 bits ? Currently I have 2 legal types in my BE, i16 and v2i16, and I could set TargetData in order to have v2i16 types with a size and alignment of 8 bits. Doing so, I will have correct address offsets but I suspect it would break optimizations phases. Any advice ? Ivan

... (ncmul >>>             (sext (i16 (extractelt RARegs:$a, imm))), >>>             (sext (i16 (extractelt RARegs:$b, imm))) >>>            ) >>>            ))), >>>           imm) ) >>> >>> where RARegs is a register class of type [i32, v2i16]. I want to match >>> that pattern in order to have one instruction which takes 2 vectors >>> (complex numbers) and gives me another vector. Unfortunately, I am >>> running into multiple tblgen type inference exceptions. I am new to llvm >>> codegen. >>>...

...))), (sext (i16 (extractelt RARegs:$b, imm))) ), (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16 (extractelt RARegs:$b, imm))) ) ))), imm) ) where RARegs is a register class of type [i32, v2i16]. I want to match that pattern in order to have one instruction which takes 2 vectors (complex numbers) and gives me another vector. Unfortunately, I am running into multiple tblgen type inference exceptions. I am new to llvm codegen. First of all, I realized that I need to explicitly cast int...

...(sext (i16 (extractelt RARegs:$a, imm))), >>>> (sext (i16 (extractelt RARegs:$b, imm))) >>>> ) >>>> ))), >>>> imm) ) >>>> >>>> where RARegs is a register class of type [i32, v2i16]. I want to match >>>> that pattern in order to have one instruction which takes 2 vectors >>>> (complex numbers) and gives me another vector. Unfortunately, I am >>>> running into multiple tblgen type inference exceptions. I am new to llvm >>>> codeg...

...6 (extractelt node:$b, (i32 0)))) ) ) >; def ADDMULv : InstSP< (outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b), "muladd $a, $b, $dst", [(set (i32 IntRegs:$dst), (mula_pat (v2i16 IntRegs:$a), (v2i16 IntRegs:$b)))]>; IntRegs is class with a type list of [i32, v2i16] But I get the following error when llvm building system try to generate the ISelector llvm[3]: Building Sparc.td DAG instruction selector implementation with tblgen vtInt: (vt:Other)<<P:Predica...

...elt RARegs:$b, imm))) >             ), >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm))), >             (sext (i16 (extractelt RARegs:$b, imm))) >            ) >            ))), >           imm) ) > > where RARegs is a register class of type [i32, v2i16]. I want to match > that pattern in order to have one instruction which takes 2 vectors > (complex numbers) and gives me another vector. Unfortunately, I am > running into multiple tblgen type inference exceptions. I am new to llvm > codegen. > > First of all, I realized that I ne...

...de >> tries to replace the SDValue with itself. >> > > I think this error can only happen during type legalization, so my guess > is that you are returning a node that has an illegal type. Can you > provide more information about the node this is failing with? On my target v2i16, v4i16, v2i32, v4i32, v2f32, v4f32 are legal and all other vector types are not. Vectors of i16 are a bit special and we need to custom lower bitcasts to/from them. Therefore we do setOperationAction(ISD::BITCAST, VT, Custom); on all MVT:s, and in our target's LowerOperation/LowerBitc...

...(ncmul >>> (sext (i16 (extractelt RARegs:$a, imm))), >>> (sext (i16 (extractelt RARegs:$b, imm))) >>> ) >>> ))), >>> imm) ) >>> >>> where RARegs is a register class of type [i32, v2i16]. I want to match >>> that pattern in order to have one instruction which takes 2 vectors >>> (complex numbers) and gives me another vector. Unfortunately, I am >>> running into multiple tblgen type inference exceptions. I am new to llvm >>> codegen. >>>...

I've added a new register class to my target, but haven't used any of the new registers in any of the instructions. However when I compile llvm I get the following error: In SFEQ_ri: Could not infer all types in pattern Curiously all the instructions where this error occurs are the set flag instructions (flags like zero, less than, greater than etc). Would anyone be able to figure out

Hi, I'm a litle bit puzzled by the TargetLowering::LowerOperation function, and what different callers of this function assumes about the returned value. In several places it seems like it is assumed that LowerOperation can return three kinds of values: * Something completely new. * SDValue() * The same SDValue as LowerOperation was called on. However in some places, e.g. in

...SDNodes, only works for registers with a unique type. My WIDE32 class caused GR32 registers to no longer have a unique type, breaking the world. This seems too fragile to me. Besides my current experiments with wide register classes, Blackfin's general purpose registers can hold both i32 and v2i16 types. Does that mean Blackfin instructions can't use GPR implicit defs as SDNode results? I would like to fix this, but I am not sure how. I could: - Disable type inference for individual registers entirely, or - Add a ValueType field to the Register tablegen class, so types are not infer...