Displaying 20 results from an estimated 399 matches for "v0".
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2012 Aug 30
1
[LLVMdev] PHI
...rify-loop-info -verify-dom-info
-verify-regalloc
# After machine block placement.
# Machine code for function main: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP-8]
fi#1: size=4, align=4, at location [SP-12]
fi#2: size=4, align=4, at location [SP-4]
Function Live Outs: %V0
BB#0: derived from LLVM BB %entry
%V0<def> = LiRxImmX16 <es:_gp_disp>[TF=5]
SaveRaF16 32
%V1<def> = AddiuRxPcImmX16 <es:_gp_disp>[TF=6]
%V0<def> = SllX16 %V0<kill>, 16
%S0<def> = AdduRxRyRz16 %V1<kill>, %V0<kill>
%...
2017 Jan 17
0
[PATCH 1/6] drm/nouveau: Extend NVKM HDMI power control method to set InfoFrames
...tions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
index ae49dfd..a3ce3bf 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
@@ -76,7 +76,21 @@ struct nv50_disp_sor_hdmi_pwr_v0 {
__u8 state;
__u8 max_ac_packet;
__u8 rekey;
- __u8 pad04[4];
+ __u8 flags;
+#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR_FLAG_AUDIO_INFOFRAME 0x01
+#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR_FLAG_AVI_INFOFRAME 0x02
+#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR_FLAG_VENDOR_INFOFRAME 0x04
+...
2013 Nov 22
0
[LLVMdev] PrologEpilogProblems;
...0; mem:ST4[FixedStack1]
ST %S0<kill>, %SP, 36; mem:ST4[FixedStack2]
PROLOG_LABEL <MCSym=_tmp1>
%S0<def> = LD %SP, 48; mem:LD4[FixedStack-1](align=8)
ST %S0, %SP, 0; mem:ST4[FixedStack-4](align=8)
JSUB <ga:@extract_l>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def>
%V1<def> = ADDI %ZERO, 1
ST %V0<kill>, %SP, 0; mem:ST4[FixedStack-5](align=8)
ST %V1<kill>, %SP, 4; mem:ST4[FixedStack-6]
JSUB <ga:@shr>, <regmask>, %LR<imp-def>, %SP<imp-def>, %V0<imp-def>
%S1<def> = LD %SP, 52; mem:LD4[FixedStac...
2017 Dec 04
0
[PATCH] drm: nouveau: use correct string length
...ne/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
index dde89a4a0f5b..53859b6254d6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
@@ -462,7 +462,7 @@ nvkm_perfmon_mthd_query_domain(struct nvkm_perfmon *perfmon,
args->v0.id = di;
args->v0.signal_nr = nvkm_perfdom_count_perfsig(dom);
- strncpy(args->v0.name, dom->name, sizeof(args->v0.name));
+ strncpy(args->v0.name, dom->name, sizeof(args->v0.name) - 1);
/* Currently only global counters (PCOUNTER) are implemented
* but t...
2012 Aug 01
2
[LLVMdev] [RFC] New command line parsing/generating framework for clang and lld.
...es, name, clang, strparse, render, rendermatch>;
class ClangFlag<string name>
: ClangOption<["-"], name, ?, "-"#name#, ?>;
class ClangSingleLetterOption<string name>
: ClangOption< ["-"], name, (or (joined (str ""), (str:$v0)),
(separate (str:$v0)))
, "-"#name#"$v0", (str:$v0)> {
int Priority = 1;
}
def clang_f_strict_enums : ClangFlag<"fstrict-enums">;
def clang_f_no_strict_enums : ClangFlag<"fno-strict-enums...
2017 Jan 17
32
[PATCH 0/6] drm/nouveau: Enable HDMI Stereoscopy
This is an initial implementation of HDMI 3D mode support for the
nouveau kernel driver. It works on all of the hardware that I have
available to test at the moment, but I am unsure as to the overall
approach taken for setting HDMI InfoFrames, there's no support for g84
or gf119 disps, and the criteria for enabling stereo support for an
output seems a bit iffy.
The first four patches arrange
2016 Oct 03
5
Is this undefined behavior optimization legal?
...ector, a common way to implement this function on a target
with 32-bit registers would be to zero initialize a 32-bit register to hold
the initial vector and then 'mask' and 'or' the inserted value with the
initial vector. In AMDGPU assembly it would look something like:
v_mov_b32 v0, 0
v_cvt_u32_f32_e32 v1, s0
v_and_b32 v1, v1, 0x000000ff
v_or_b32 v0, v0, v1
The optimization the SelectionDAG does for us in this function, though, ends
up removing the mask operation. Which gives us:
v_mov_b32 v0, 0
v_cvt_u32_f32_e32 v1, s0
v_or_b32 v0, v0, v1
The reason the SelectionDAG is d...
2004 Sep 10
1
altivec lpc_restore_signal
...data
slwi r6,r6,2 ; adjust for word size
slwi r4,r4,2
add r4,r4,r8 ; r4 = data+data_len
mfspr r0,256 ; cache old vrsave
addis r31,0,hi16(0xfffffc00)
ori r31,r31,lo16(0xfffffc00)
mtspr 256,r31 ; declare VRs in vrsave
cmplw cr0,r8,r4 ; i<data_len
bc 4,0,L1400
; load coefficients into v0-v7 and initial history into v8-v15
li r31,0xf
and r31,r8,r31 ; r31: data%4
li r11,16
subf r31,r31,r11 ; r31: 4-(data%4)
slwi r31,r31,3 ; convert to bits for vsro
li r10,-4
stw r31,-4(r9)
lvewx v0,r10,r9
vspltisb v18,-1
vsro v18,v18,v0 ; v18: mask vector
li r31,0x8
lvsl v0,0,r31
vsldoi...
2017 Aug 29
1
glfsheal-v0.log Too many open files
Sorry, I send the mail to devel group by mistake..
Any help about the below issue?
On Tue, Aug 29, 2017 at 3:00 PM, Serkan ?oban <cobanserkan at gmail.com> wrote:
> Hi,
>
> When I run gluster v heal v0 info, it gives "v0: Not able to fetch
> volfile from glusterd" error message.
> I see too many open files errors in glfsheal-v0.log file. How can I
> increase open file limit for glfsheal?
> I already increased nfile limit in /etc/init.d/glusterd and
> /etc/init.d/gluserfsd...
2016 Jun 24
6
RFC: Strong GC References in LLVM
...* %ptr
== Transformed to ==>
%value = load i64, i64* %ptr
%value_gc = inttoptr %value to GCREF (%value_gc unused)
is invalid for the same reason.
## GCREF -> Integer conversion
Converting a GCREF to an integer is fine if the integer is unused.
However, cases like these are problematic:
%v0 = load GCREF, GCREF* %ptr_0
%v1 = load GCREF, GCREF* %ptr_1
%cmp = icmp eq %v0, %v1
== Transformed to ==>
%v0 = load i64, i64* %ptr_0
%v1 = load i64, i64* %ptr_1
%cmp = icmp eq %v0, %v1
Since in the second version if "L" is, say, between %v0 and %v1, "G"
would not include &q...
2010 Feb 18
1
an error about " return some vectors from some functions within a function"
...:
###################
# functions in the convg #
###################
check1 <- function(sumgt,beta1.0,gamma.0,sigma.0){
if (any(!is.finite(sumgt))){
count1 <- count1+1
return(c(count1,beta1.0,gamma.0,sigma.0))
}
else {return(c(NaN,NaN,NaN,NaN))}
}
check2 <- function(v0,maxit,iter,beta1.0,gamma.0,sigma.0){
if (is.nan(sum(v0))==TRUE | any(!is.finite(v0)) | maxit == iter){
count1 <- count1+1
return(c(count1,beta1.0,gamma.0,sigma.0))
}
else {return(c(NaN,NaN,NaN,NaN))}
}
check3 <- function(maxit,diff,error,beta1.0,gamma.0,sigma.0){
...
2013 Nov 11
2
[LLVMdev] What's the Alias Analysis does clang use ?
...eems not to tell must-not-alias for __restrict__ arguments
in c/c++. It only compares two pointers and the underlying objects they
point to. I wonder how clang does alias analysis
for c/c++ keyword restrict.
let assume we compile the following code:
$cat myalias.cc
float foo(float * __restrict__ v0, float * __restrict__ v1, float *
__restrict__ v2, float * __restrict__ t) {
float res;
for (int i=0; i<10; ++i) {
float x = v0[1];
float y = v1[1];
float z = v2[1];
res = x * 0.67 + y * 0.17 + z * 0.16;...
2012 Aug 09
0
[LLVMdev] [RFC] New command line parsing/generating framework for clang and lld.
...ender, rendermatch>;
>
> class ClangFlag<string name>
> : ClangOption<["-"], name, ?, "-"#name#, ?>;
>
> class ClangSingleLetterOption<string name>
> : ClangOption< ["-"], name, (or (joined (str ""), (str:$v0)),
> (separate (str:$v0)))
> , "-"#name#"$v0", (str:$v0)> {
> int Priority = 1;
> }
>
> def clang_f_strict_enums : ClangFlag<"fstrict-enums">;
> def clang_f_no_strict_enums : C...
2003 Apr 07
1
Problems building the java/jdk14 port
...ution, and get some weird HotSpot error.
I am not sure what the problem could be. Following is the relevant
output of make on the port.
Any ideas?
-- Tom
# Start of jdk build
bsd i586 1.4.1-p3 build started: 03-04-07 12:16
Syntax error: "(" unexpected
gmake[1]: Entering directory `/v0/pobj/r+d/ports/java/jdk14/work/j2se/make'
[: -ne: unexpected operator
gmake[1]: Leaving directory `/v0/pobj/r+d/ports/java/jdk14/work/j2se/make'
if [ -r ./../../patch/make/Makefile ]; then \
( cd ./../../patch/make; gmake sanity MAKEFLAGS= EXTERNALSANITYCONTROL=true CONTROL_TOPDIR=/v0/po...
2016 Sep 19
3
[arm, aarch64] Alignment checking in interleaved access pass
Hi,
As a follow up to Patch D23646 <https://reviews.llvm.org/D23646>, I'm
trying to figure out if there should be an alignment check and what the
correct approach is.
Some background:
For stores, the pass turns:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
<0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
Into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>...
2004 Oct 06
3
flac-1.1.1 completely broken on linux/ppc and on macosx if built with the standard toolchain (not xcode)
Sadly the latest optimization broke completely everything.
The asm code isn't gas compliant. the libFLAC linker script has a typo,
disabling the asm optimization and/or altivec won't let a correct build
anyway.
Instant fixes for the asm stuff:
sed -i -e"s:;:\#:" on the lpc_asm.s
to load address instead of addis+ori you could use
lis and la and PLEASE use the @l(register)
2013 Nov 12
0
[LLVMdev] What's the Alias Analysis does clang use ?
Hi,
Your problem is that the function arguments, which are makes as noalias, are not being directly used as the base objects of the array accesses:
> %v0.addr = alloca float*, align 8
> %v1.addr = alloca float*, align 8
> %v2.addr = alloca float*, align 8
> %t.addr = alloca float*, align 8
...
> store float* %v0, float** %v0.addr, align 8
> store float* %v1, float** %v1.addr, align 8
> store float* %v2, float** %v2.addr, align 8
&g...
2011 Aug 18
3
Error message: object of type 'closure' is not subsettable
Dear R-users
I need to calibrate kappa, rho, eta, theta, v0 in the following code, see
below. However when I run it, I get:
y <- function(kappahat, rhohat, etahat, thetahat, v0hat) {sum(difference(k,
t, S0, X, r, implvol, q, kappahat, rhohat, etahat, thetahat, v0hat)^2)}
> nlminb(start=list(kappa, rho, eta, theta, v0), objective = y, lower =lb,
>...
2013 Nov 28
2
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...=========================================================================
> --- llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt Wed Nov 27 19:07:45 2013
> @@ -2129,7 +2129,8 @@
> # CHECK: ld1 {v0.b}[9], [x0], #1
> # CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
> # CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
> -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24
> +# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
> +# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0
> #...
2016 Apr 20
2
[PATCH v4 27/37] clk: make pstate a pointer to nvkm_pstate
...trl.c b/drm/nouveau/nvkm/engine/device/ctrl.c
> index 039e8a4..cb85266 100644
> --- a/drm/nouveau/nvkm/engine/device/ctrl.c
> +++ b/drm/nouveau/nvkm/engine/device/ctrl.c
> @@ -52,7 +52,10 @@ nvkm_control_mthd_pstate_info(struct nvkm_control *ctrl, void *data, u32 size)
> args->v0.ustate_ac = clk->ustate_ac;
> args->v0.ustate_dc = clk->ustate_dc;
> args->v0.pwrsrc = clk->pwrsrc;
> - args->v0.pstate = clk->pstate;
> + if (clk->pstate)
> + args->v0.pstate = clk->pstate->pstate;
> + else
> + args->v0.pstate...