search for: vr0

...39;s ipfw for quite a while and recently on a new server i've got this issue with ipfw that i can't understand ... something is wrong ... 01000 8042 1947866 allow ip from any to any via fxp0 01010 0 0 allow ip from any to any via lo0 01014 9886 4170269 divert 8668 ip from any to any in via vr0 01015 0 0 check-state 01130 14679 5695969 skipto 1800 ip from any to any out via vr0 keep-state 01300 0 0 deny ip from 192.168.0.0/16 <http://192.168.0.0/16> to any in via vr0 01301 0 0 deny ip from 172.16.0.0/12 <http://172.16.0.0/12> to any in via vr0 01302 4 140 deny ip from 10.0.0.0...

Hello, My computer is not connecting to the local network with the following configuration: dmesg.boot contains the following lines: ----------------------------------------- vr0: <VIA VT3043 Rhine I 10/100BaseTX> port 0xec00-0xec7f mem 0xfeafbc00-0xfeafbc7f irq 11 at device 12.0 on pci2 vr0: Ethernet address: 00:40:05:a5:00:04 miibus0: <MII bus> on vr0 amphy0: <Am79C873 10/100 media interface> on miibus0 amphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX...

...e just fine. This problem is similar to that of two-address constraints. Two address instructions work as follows. When we match an instruction we “tie” input and output registers. Say you had an LLVM-IR add: x = add i32 y, z for x86 we generate the following machine ir instruction during ISel: vr0<def, tied1> = ADD32rr vr1<use, tied0>, vr2<use> Once we go out of SSA during CodeGen we have to replace the two address constraint by copies: vr0 = vr1 vr0 = ADD32rr vr0, vr2 Coalescing and allocation will then take care of removing unnecessary copies. I think that predicate in...

...ined registers and a new type(vpr) for vector predicate registers in backend. Although there is no direct instruction to move vpr to vr or to move vr to vpr, there is a method to work around this. And we have load/store instructions for vr. move vpr to vr for v32i16 (from vpr0 to vr1): 1 vclr vr0 // clear vr0 2 ldi r5, 0x00010001 // load immediate (compare bit mask for v32i16) to scalar register r5 3 movr2vr.dup vr2, r5 // duplicate content in r5 into vr2, 4 vadd.t.s16 vr1, vr0, vr2, vpr0 //vector add if element compare bit is set, element type is 16 bit signed integ...

...to that of two-address constraints. Two address instructions work as follows. When we match an instruction we “tie” input and output registers. > > Say you had an LLVM-IR add: > > x = add i32 y, z > > for x86 we generate the following machine ir instruction during ISel: > > vr0<def, tied1> = ADD32rr vr1<use, tied0>, vr2<use> > > Once we go out of SSA during CodeGen we have to replace the two address constraint by copies: > > vr0 = vr1 > vr0 = ADD32rr vr0, vr2 > > Coalescing and allocation will then take care of removing unnecessary c...

...ined registers and a new type(vpr) for vector predicate registers in backend. Although there is no direct instruction to move vpr to vr or to move vr to vpr, there is a method to work around this. And we have load/store instructions for vr. move vpr to vr for v32i16 (from vpr0 to vr1): 1 vclr vr0 // clear vr0 2 ldi r5, 0x00010001 // load immediate (compare bit mask for v32i16) to scalar register r5 3 movr2vr.dup vr2, r5 // duplicate content in r5 into vr2, 4 vadd.t.s16 vr1, vr0, vr2, vpr0 //vector add if element compare bit is set, element type is 16 bit signed integ...

On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether

...appens during coalescing and live range splitting. Virtual-to-physical rewriting happens only once at the end. When rewriting virtual registers, a minimal understanding of value semantics is required. In particular, it is possible to split a live range right down the middle of an instruction: %vr0 = add %vr0, 1 May be rewritten as: %vr2 = add %vr1, 1 This is assuming the add doesn't have two-address constraints, of course. When rewriting bundle operands, the <internal> flag will be sufficient to determine the correct virtual register. For example: { %vr0 = cmp.eq(R2,#4)...

...), 30 deletions(-) diff --git a/Documentation/mic/mpssd/mpssd.c b/Documentation/mic/mpssd/mpssd.c index 5c7fdda..befc2c3 100644 --- a/Documentation/mic/mpssd/mpssd.c +++ b/Documentation/mic/mpssd/mpssd.c @@ -445,8 +445,8 @@ init_vr(struct mic_info *mic, int fd, int type, __func__, mic->name, vr0->va, vr0->info, vr_size, vring_size(MIC_VRING_ENTRIES, MIC_VIRTIO_RING_ALIGN)); mpsslog("magic 0x%x expected 0x%x\n", - vr0->info->magic, MIC_MAGIC + type); - assert(vr0->info->magic == MIC_MAGIC + type); + le32toh(vr0->info->magic), MIC_MAGIC + type); + ass...

...), 30 deletions(-) diff --git a/Documentation/mic/mpssd/mpssd.c b/Documentation/mic/mpssd/mpssd.c index 5c7fdda..befc2c3 100644 --- a/Documentation/mic/mpssd/mpssd.c +++ b/Documentation/mic/mpssd/mpssd.c @@ -445,8 +445,8 @@ init_vr(struct mic_info *mic, int fd, int type, __func__, mic->name, vr0->va, vr0->info, vr_size, vring_size(MIC_VRING_ENTRIES, MIC_VIRTIO_RING_ALIGN)); mpsslog("magic 0x%x expected 0x%x\n", - vr0->info->magic, MIC_MAGIC + type); - assert(vr0->info->magic == MIC_MAGIC + type); + le32toh(vr0->info->magic), MIC_MAGIC + type); + ass...

I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the

This note is essentially a request for a reality check. I use IPFW & natd on the box that provides the interface between my home networks and the Internet; the connection is (static) residential DSL. I configured IPFW to accept & log all SSH "setup" requests, and use natd to forward such requests to an internal machine that only accepts public key authentication; that

...<ISA bus> on isab0 atapci0: <VIA 8235 ATA133 controller> port 0xfc00-0xfc0f at device 17.1 on pci0 ata0: at 0x1f0 irq 14 on atapci0 ata1: at 0x170 irq 15 on atapci0 pcm0: <VIA VT8235> port 0xdc00-0xdcff irq 11 at device 17.5 on pci0 pcm0: <unknown ac97 codec> (id=0x56494161) vr0: <VIA VT6102 Rhine II 10/100BaseTX> port 0xd800-0xd8ff mem 0xdffffd00-0xdffffdff irq 11 at device 18.0 on pci0 vr0: Ethernet address: 00:e0:18:ad:3a:7f miibus1: <MII bus> on vr0 ukphy0: <Generic IEEE 802.3u media interface> on miibus1 ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100b...

...ds to the "Bundle" pseudo MI. This allows all later passes to handle they transparently. However, we do not want to do this before register allocation is complete. Otherwise it introduces new defs and uses of virtual registers and that mess up MachineRegisterInfo def-use chains. e.g. Now vr0 has two defs! defs: vr0<dead>, vr3, uses: vr1, vr2 ---------------------------- | vr0 = op1 vr1, vr2 | | vr3 = op2 vr0<kill>, #c | ---------------------------- 2. During register allocation, more identity copies will be eliminated while loads, stores, copies, re-materialized ins...

...sb0 usb1 usb2 usb3 usb4: <VIA VT6202 USB 2.0 controller> on ehci0 usb4: USB revision 2.0 uhub4: <VIA EHCI root hub, class 9/0, rev 2.00/1.00, addr 1> on usb4 uhub4: 8 ports with 8 removable, self powered isab0: <PCI-ISA bridge> at device 17.0 on pci0 isa0: <ISA bus> on isab0 vr0: <VIA VT6102 Rhine II 10/100BaseTX> port 0xe400-0xe4ff mem 0xe1044000-0xe10440ff irq 23 at device 18.0 on pci0 vr0: Quirks: 0x0 vr0: Revision: 0x78 miibus0: <MII bus> on vr0 ukphy0: <Generic IEEE 802.3u media interface> PHY 1 on miibus0 ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 1...

...to the "Bundle" pseudo MI. This allows all later passes to handle they transparently. However, we do not want to do this before register allocation is complete. Otherwise it introduces new defs and uses of virtual registers and that mess up MachineRegisterInfo def-use chains. e.g. Now vr0 has two defs! defs: vr0<dead>, vr3, uses: vr1, vr2 ---------------------------- | vr0 = op1 vr1, vr2 | | vr3 = op2 vr0<kill>, #c | ---------------------------- 2. During register allocation, more identity copies will be eliminated while loads, stores, copies, re-material...

...quot;Bundle" pseudo MI. This allows all later passes to handle they transparently. However, we do not want to do this before register allocation is complete. Otherwise it introduces new defs and uses of virtual registers and that mess up MachineRegisterInfo def-use chains. > > e.g. Now vr0 has two defs! > defs: vr0<dead>, vr3, uses: vr1, vr2 > ---------------------------- > | vr0 = op1 vr1, vr2 | > | vr3 = op2 vr0<kill>, #c | > ---------------------------- > > 2. During register allocation, more identity copies will be eliminated while loads,...

...to the "Bundle" pseudo MI. This allows all later passes to handle they transparently. However, we do not want to do this before register allocation is complete. Otherwise it introduces new defs and uses of virtual registers and that mess up MachineRegisterInfo def-use chains. e.g. Now vr0 has two defs! defs: vr0<dead>, vr3, uses: vr1, vr2 ---------------------------- | vr0 = op1 vr1, vr2 | | vr3 = op2 vr0<kill>, #c | ---------------------------- 2. During register allocation, more identity copies will be eliminated while loads, stores, copies, re-material...

...ds to the "Bundle" pseudo MI. This allows all later passes to handle they transparently. However, we do not want to do this before register allocation is complete. Otherwise it introduces new defs and uses of virtual registers and that mess up MachineRegisterInfo def-use chains. e.g. Now vr0 has two defs! defs: vr0<dead>, vr3, uses: vr1, vr2 ---------------------------- | vr0 = op1 vr1, vr2 | | vr3 = op2 vr0<kill>, #c | ---------------------------- 2. During register allocation, more identity copies will be eliminated while loads, stores, copies, re-materialized ins...

..., align 2 br label %5 ;<label>:5 %6 = load i16 *a, align 2 store i16 %6, i16 c I used getCopyToReg in SelectionDAG for store instruction to store value, and getCopyFromReg for load instruction. So, storage values in block '<label>:3' and '<label>:4' are stored in VR0 and VR1 respectively. However, load instruction in block '<label>:5' cannot choose which register should be read. Can anybody give an idea to overcome such a case? Thanks. Jin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/p...