Displaying 6 results from an estimated 6 matches for "uimm16".
Did you mean:
simm16
2017 Feb 15
4
Unsigned int displaying as negative
I see. If I put simm16 and immSExt16x in place of uimm16 and immZExt16x
respectively, the imm matches but it prints out -32768 (which is invalid
for sub16u). We are using uimm16 not match unsigned but for PrintMethod,
effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why
simm16 matches and uimm16 does not. Here is the patte...
2017 Feb 15
5
Unsigned int displaying as negative
Where does the unsignedSub come from?
On 2017-02-15 20:38, Ryan Taylor wrote:
> Sorry, it should be:
>
> defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs,
> GPRRegs, DSTRegs, i16, i16, i16, uimm16, immZExt16x>;
>
> On Wed, Feb 15, 2017 at 2:37 PM, Ryan Taylor <ryta1203 at gmail.com>
> wrote:
>
>> I see. If I put simm16 and immSExt16x in place of uimm16 and
>> immZExt16x
>> respectively, the imm matches but it prints out -32768 (which is
>> in...
2017 Feb 15
2
Unsigned int displaying as negative
Thanks for your reply.
We are propagating sign info to tablegen currently using
BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm.
I imagine (I have not looked) they are printed according to instruction in
AsmPrinter.cpp (pure speculation).
I'm still confused as to why 0x7FFF is ok to match 16 bit int but not
0x8000?
Thanks.
On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at
2008 Sep 15
1
[LLVMdev] Prevent a intrinsic to be reordered?
...in MIPS):
class SORUI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: FI<op, outs, ins, asmstr, pattern, itin>
{
let isBarrier = 1; // or call, hassideefects, ..., nothing work
}
def SORU_SRE: SORUI<0b110011, (outs), (ins uimm16:$imm), "sre $imm",
[(int_soru_sre imm:$imm)], IISoru>;
(With IISoru I made all the possible changes: a lot of cycles or none with
all the functional units or none)
And an example:
tail call void @llvm.soru.sre( i32 5 )
mul i32 %b, %a ; <i32>:0 [#us...
2008 Sep 14
0
[LLVMdev] Prevent a intrinsic to be reordered?
Hello, Julio
> These later things are ignored, I don't know if when the intrinsic is
> lowered, then it doesn't matter (or perhaps the reorder is made
> before).
What is the description of the instruction you're lowering intrinsic
into? Have you looked for the instruction flags defined in Target.td
file? You instruction should definitely have "isBarrier" flag set.
2008 Sep 14
3
[LLVMdev] Prevent a intrinsic to be reordered?
Hello, I have an intrinsic that matches to a asm instruction directly. This
intrinsic starts a coprocessor that can do anything.
If I put another instruction next to it (a multiplication for example), the
"llc" reorders and puts the intrinsic after the multiplication.
I have tried all:
- Setting the instruction like if it takes 256 cycles or 0 cycles.
- Setting the instruction with