search for: simm16

...e case. This isn't just the results of instructions, but also immediate values as well. It seems to affect a smattering of node types. Any insights? For instance: where GPRegs contains types [i32, f32] def BEQ : IF8<Opc.BEQ, (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), "beq $Rsrc1, $Rsrc2, $SImm16", [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: $SImm16)], s_br>; Tablegen reports: BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, SETEQ:Other), (bb:Other):$SImm16) as soon as I add a regist...

Hi all, I want to match addition with 16bit integers. So I define a pattern fragment as follows: def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; Now I am confused between (add R32:$dst, simm16:$im) and (add R32:$dst, (i32 simm16:$im)). Do both of them match the same pattern? Are they equivalent? If not what is the difference? I am also confused as to how ValueTyp...

...lts of instructions, but also immediate > values as well. It seems to affect a smattering of node types. Any > insights? > > For instance: > > where GPRegs contains types [i32, f32] > > def BEQ : IF8<Opc.BEQ, > (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), > "beq $Rsrc1, $Rsrc2, $SImm16", > [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: > $SImm16)], s_br>; > > Tablegen reports: > BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, > SETEQ:Other), (bb:Other):$SImm1...

I see. If I put simm16 and immSExt16x in place of uimm16 and immZExt16x respectively, the imm matches but it prints out -32768 (which is invalid for sub16u). We are using uimm16 not match unsigned but for PrintMethod, effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why simm16 matches and...

..., it should be: > > defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, > GPRRegs, DSTRegs, i16, i16, i16, uimm16, immZExt16x>; > > On Wed, Feb 15, 2017 at 2:37 PM, Ryan Taylor <ryta1203 at gmail.com> > wrote: > >> I see. If I put simm16 and immSExt16x in place of uimm16 and >> immZExt16x >> respectively, the imm matches but it prints out -32768 (which is >> invalid >> for sub16u). We are using uimm16 not match unsigned but for >> PrintMethod, >> effectively uimm16 and simm16 are both Operand&...

...ate >> values as well. It seems to affect a smattering of node types. Any >> insights? >> >> For instance: >> >> where GPRegs contains types [i32, f32] >> >> def BEQ : IF8<Opc.BEQ, >> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), >> "beq $Rsrc1, $Rsrc2, $SImm16", >> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: >> $SImm16)], s_br>; >> >> Tablegen reports: >> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, >> SET...

...of instructions, but also immediate > values as well. It seems to affect a smattering of node types. Any > insights? > > For instance: > > where GPRegs contains types [i32, f32] > > def BEQ : IF8<Opc.BEQ, > (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), > "beq $Rsrc1, $Rsrc2, $SImm16", > [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: > $SImm16)], s_br>; > > Tablegen reports: > BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32: > $Rsrc2, SETEQ:Other), (bb:Other):$SI...

...VM using the Mips Target as a base. Coming along quite well, currently ran into two problems with my sample/test program. The main issue I am having is with respect to the following (Note: I have already changed ADDui from ADDiu) We have this def ADDui : ArithI<0x09, "addui", add, simm16, immSExt16>; However sticky speaking this should be in dlx the instructions are addui rk, ri, Kuns (Where Kusn is unsigned) Likewise DLX has a subui rk, ri, Kusn. (Mips does not) Thus they should be: def ADDui : ArithI<0x09, "addui", add, simm16, immZExt16>; def SUBui : Ar...

...le to do this using only TableGen ? I assume that I should only define a class in TARGETInstrInfo.td file. Currently I have done the following: in TARGETRegisterInfo.td file I have defined the registers: MYREG1_NAME and MYREG2_NAME in TARGETInstrInfo.td file I have the following definitions: def simm16 : Operand<i16> { let DecoderMethod= "DecodeSimm16"; let OperandType = "OPERAND_IMMEDIATE"; } class SII<bits&lt;6> op, string instr_asm, Operand Imm> : FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm, &quot;\t$val&quot;), [], I...

Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at

Hmm, I'm getting nowhere pretty fast. It seems 68000 with its CISC nature is quite complex to implement for a novice. I can see how to implement simple stuff, like -- move dn, dn move dn, (an) As that just turns into stores, sets, etc. But how would you represent things like indexed access? move dn, (an,dn) move dn, offset(an) Can I only really define very simple operations for the main

Hi Johnny, Thank you for your help. I guess the pseudo instruction does not interfere in the generated assembly code. I'll check the file that describes the registers and I hope understand why the assembly code is printed wrong (now is printed things like add r1, r0, -40). Cheers, Carlos Carlos Almeida Jr On Thu, Nov 27, 2014 at 7:56 AM, Johnny Val <johnnydval at gmail.com> wrote:

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPRegs, GPRegs); let EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, &quot...

...the fundamental structure from existing backends, e.g., what is necessary for an early stage and what is the refined result after years of development. For example, everything went well with Cpu0RegisterInfo.td, with only a little struggle. But for Cpu0InstrInfo.td, questions start to come up: Why simm16 is inherited from Operand<i32>? What are PatLeaf and ComplexPattern? What is isReMaterializable? etc. Every line of description, every occurrence of new keyword or concept would confuse a beginner reader. They need to find enough information to follow this tutorial. This tutorial seems to tel...

...d memory with 32-bit signed offset         gslbx           $2,0($3,$4)                                       ^ I just copy-n-paste  mem_generic  and  getMemEncoding: def gs_mem : Operand<iPTR> {   let PrintMethod = "printMemOperand";   let MIOperandInfo = (ops ptr_rc, ptr_rc, simm16); ^-- for two registers   let EncoderMethod = "getGSMemEncoding";                                             ^-- just encoding two registers and one offset   let ParserMatchClass = MipsMemAsmOperand;   let OperandType = "OPERAND_MEMORY"; } ----- 8< -------- 8< ---...

I was wondering if this shouldn't somehow find its way into the official LLVM documentation? It certainly seems to qualify to become official documentation in my eyes. Nearly any LLVM backend writer out there should be able to benefit from reading about your experiences, I'd think. I know it is not as generic and abstract as what the LLVM dev list seems to prefer, but I personally find

Hi, I am writing an llvm backend tutorial through my learning process of llvm backend study and implementation. Web as follows, http://jonathan2251.github.com/lbd/index.html It include 10,000 lines of sources code for 1. Step by step, create an llvm backend for the Cpu0 which beginning from a CPU design for school teaching purpose in system programming. 2. ELF linker for Cpu0 which extended

...AReg:$srcA)), addr16:$dstD)]>; def MEM_MEM : SetADIn<asmstr, memhx, memhx, [(directStore (dstType (OpNode (srcAType (load addr16:$srcA)))), addr16:$dstD)]>; } defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, i16, i16, simm16, immSExt16x>; On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Quentin, > > 1. I'll take a look, it's also picking the reg class by the > SimpleValueType and then getting the common subclass. Choosing to constrain > the reg class to G...

...> def MEM_MEM : SetADIn<asmstr, memhx, memhx, > [(directStore (dstType (OpNode (srcAType > (load addr16:$srcA)))), addr16:$dstD)]>; > } > > defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, > i16, i16, simm16, immSExt16x>; > > > What is defining VReg? > It is AD or is it MOV16Copy? > > Also what are the arguments of the multiclass AD that you match? > > > On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > >> Quentin, >> >&g...

...SetADIn<asmstr, memhx, memhx, >> [(directStore (dstType (OpNode (srcAType >> (load addr16:$srcA)))), addr16:$dstD)]>; >> } >> >> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, >> i16, i16, simm16, immSExt16x>; >> >> >> What is defining VReg? >> It is AD or is it MOV16Copy? >> >> Also what are the arguments of the multiclass AD that you match? >> >> >> On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: &g...