search for: tseg

...f (!strcmp(".smp_locks", secstrings + s->sh_name)) locks= s; + if (!strcmp(".parainstructions", secstrings + s->sh_name)) + para = s; } if (alt) { @@ -132,6 +135,10 @@ int module_finalize(const Elf_Ehdr *hdr, lseg, lseg + locks->sh_size, tseg, tseg + text->sh_size); } + if (para) { + void *aseg = (void *)alt->sh_addr; + apply_paravirt(aseg, aseg + alt->sh_size); + } return 0; } diff -urpN --exclude TAGS -X /home/rusty/devel/kernel/kernel-patches/current-dontdiff --minimal working-2.6.17-rc4-function-call-abstraction/ar...

...f (!strcmp(".smp_locks", secstrings + s->sh_name)) locks= s; + if (!strcmp(".parainstructions", secstrings + s->sh_name)) + para = s; } if (alt) { @@ -132,6 +135,10 @@ int module_finalize(const Elf_Ehdr *hdr, lseg, lseg + locks->sh_size, tseg, tseg + text->sh_size); } + if (para) { + void *aseg = (void *)alt->sh_addr; + apply_paravirt(aseg, aseg + alt->sh_size); + } return 0; } diff -urpN --exclude TAGS -X /home/rusty/devel/kernel/kernel-patches/current-dontdiff --minimal working-2.6.17-rc4-function-call-abstraction/ar...

...t;sh_addr; apply_alternatives(aseg, aseg + alt->sh_size); } + if (pv_alt) { + /* patch .altinstructions */ + void *seg = (void *)pv_alt->sh_addr; + apply_alternatives(seg, seg + pv_alt->sh_size); + } if (locks && text) { void *lseg = (void *)locks->sh_addr; void *tseg = (void *)text->sh_addr; diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index f05f00acac89..94537de39109 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -250,6 +250,12 @@ SECTIONS *(.altinstructions) __alt_instructions_end = .;...

OK, this is the revised paravirt.h (Andi has seen this before), then the second is the binary patching stuff. More things get added to the paravirt struct in future patches, but this basic stuff hasn't changed for some time. ==== This patch does the dumbest possible replacement of paravirtualized instructions: calls through a "paravirt_ops" structure. Currently these are function

...2500.084 MHz processor. Calibrating delay loop (skipped), value calculated using timer frequency.. 5000.16 BogoMIPS (lpj=10000324) Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) Mount-cache hash table entries: 256 tseg: 0000000000 CPU: Physical Processor ID: 0 CPU: Processor Core ID: 0 mce: CPU supports 6 MCE banks Performance Events: AMD PMU driver. ... version: 0 ... bit width: 48 ... generic registers: 4 ... value mask: 0000ffffffffffff ... max period: 0...

...subsys devices [ 0.005769] Initializing cgroup subsys freezer [ 0.005774] Initializing cgroup subsys net_cls [ 0.005807] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) [ 0.005813] CPU: L2 Cache: 512K (64 bytes/line) [ 0.005819] CPU 0/0x0 -> Node 0 [ 0.005824] tseg: 00d7f00000 [ 0.005827] CPU: Physical Processor ID: 0 [ 0.005831] CPU: Processor Core ID: 0 [ 0.005836] mce: CPU supports 6 MCE banks [ 0.005855] Performance Events: AMD PMU driver. [ 0.005861] ------------[ cut here ]------------ [ 0.005870] WARNING: at arch/x86/xen/enlighten.c:7...

The following patches introduce the core infrastructure needed to paravirtualize the 32-bit x86 Linux kernel. This is done by moving virtualization sensitive insn's or code paths to a function table, paravirt_ops. This structure can be populated with hypervisor specific calls or native stubs and currently support running on bare metal, VMI, Xen, or Lhype. These patches apply to

The following patches introduce the core infrastructure needed to paravirtualize the 32-bit x86 Linux kernel. This is done by moving virtualization sensitive insn's or code paths to a function table, paravirt_ops. This structure can be populated with hypervisor specific calls or native stubs and currently support running on bare metal, VMI, Xen, or Lhype. These patches apply to

...unt-cache hash table entries: 256 [ 0.003146] Initializing cgroup subsys devices [ 0.003153] Initializing cgroup subsys freezer [ 0.003157] Initializing cgroup subsys net_cls [ 0.003161] Initializing cgroup subsys blkio [ 0.003165] Initializing cgroup subsys perf_event [ 0.003209] tseg: 0000000000 [ 0.003223] mce: CPU supports 5 MCE banks [ 0.003238] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 4 [ 0.003238] Last level dTLB entries: 4KB 512, 2MB 8, 4MB 4, 1GB 0 [ 0.003238] tlb_flushall_shift: 6 [ 0.010532] ..TIMER: vector=0x30 apic1=0 pin1=0 apic2=-1 pin2=-1 [ 0...

...Initializing cgroup subsys memory [ 0.006125] Initializing cgroup subsys devices [ 0.006128] Initializing cgroup subsys freezer [ 0.006132] Initializing cgroup subsys net_cls [ 0.006135] Initializing cgroup subsys blkio [ 0.006147] Initializing cgroup subsys perf_event [ 0.006184] tseg: 0000000000 [ 0.006208] CPU: Physical Processor ID: 0 [ 0.006210] CPU: Processor Core ID: 0 [ 0.006212] mce: CPU supports 5 MCE banks [ 0.006224] using AMD E400 aware idle routine [ 0.006553] ACPI: Core revision 20110623 [ 0.012524] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin...

I was using my computer normally when suddenly my btrfs volume became read-only. This is on Chris'' for-linus branch (latest commit cb77fcd88) Here''s the relevant excerpt from dmesg [ 50.877500] r8169 0000:01:00.0: eth1: link up [ 50.880296] ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 60.959215] eth1: no IPv6 routers present [ 1904.463247] atkbd serio0: Unknown key

Hello! I'm having problems getting PCI pass-through to work. This is on a AMD64 system, paravirtualized with xen-hypervisor-4.0-amd64 4.0.0-1~experimental.1, dom0: linux-image-2.6.32-5-xen-amd64 2.6.32-12. From IRC, earlier today: <tschwinge> waldi: Aren't the Debian xen domU-capable kernels supposed to contain the PCI frontend (needed for PCI pass-through)? I'm getting:

Hello! I'm having problems getting PCI pass-through to work. This is on a AMD64 system, paravirtualized with xen-hypervisor-4.0-amd64 4.0.0-1~experimental.1, dom0: linux-image-2.6.32-5-xen-amd64 2.6.32-12. From IRC, earlier today: <tschwinge> waldi: Aren't the Debian xen domU-capable kernels supposed to contain the PCI frontend (needed for PCI pass-through)? I'm getting:

...Initializing cgroup subsys memory [ 4.545005] Initializing cgroup subsys devices [ 4.545009] Initializing cgroup subsys freezer [ 4.545013] Initializing cgroup subsys net_cls [ 4.545017] Initializing cgroup subsys blkio [ 4.545019] Initializing cgroup subsys perf_event [ 4.545077] tseg: 00bd800000 [ 4.545081] CPU: Physical Processor ID: 0 [ 4.545083] CPU: Processor Core ID: 0 [ 4.545087] mce: CPU supports 2 MCE banks [ 4.545104] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512 [ 4.545104] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 512 [ 4.545104] tlb_fl...

...er > [ 0.015422] Initializing cgroup subsys net_cls > [ 0.015426] Initializing cgroup subsys blkio > [ 0.015430] Initializing cgroup subsys perf_event > [ 0.015432] Initializing cgroup subsys net_prio > [ 0.015439] Initializing cgroup subsys hugetlb > [ 0.015456] tseg: 0000000000 > [ 0.015460] CPU: Physical Processor ID: 0 > [ 0.015462] CPU: Processor Core ID: 0 > [ 0.015464] mce: CPU supports 7 MCE banks > [ 0.015470] LVT offset 1 assigned for vector 0xf9 > [ 0.015475] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512 > [ 0...

This changes the pv ops code generation to more closely match reality. For example, instead of: callq *0xffffffff81e3a400 (pv_irq_ops.save_fl) vmlinux will now show: pushfq pop %rax nop nop nop nop nop which is what the runtime version of the code will show in most cases. This idea was suggested by Andy Lutomirski. The benefits are: - For the most common runtime cases

This changes the pv ops code generation to more closely match reality. For example, instead of: callq *0xffffffff81e3a400 (pv_irq_ops.save_fl) vmlinux will now show: pushfq pop %rax nop nop nop nop nop which is what the runtime version of the code will show in most cases. This idea was suggested by Andy Lutomirski. The benefits are: - For the most common runtime cases

Hi, another issue I''m seeing with 3.0-rc2 and Xen is that there is an unexpectedly high amount of kernel reserved memory. I suspect that Linux allocates page table entries and corresponding data structures for the whole 6GB areas of the provided ''physical RAM map'' even though it has rather big unusable holes in it. [ 0.000000] BIOS-provided physical RAM map: [

...itializing cgroup subsys freezer [ 0.015422] Initializing cgroup subsys net_cls [ 0.015426] Initializing cgroup subsys blkio [ 0.015430] Initializing cgroup subsys perf_event [ 0.015432] Initializing cgroup subsys net_prio [ 0.015439] Initializing cgroup subsys hugetlb [ 0.015456] tseg: 0000000000 [ 0.015460] CPU: Physical Processor ID: 0 [ 0.015462] CPU: Processor Core ID: 0 [ 0.015464] mce: CPU supports 7 MCE banks [ 0.015470] LVT offset 1 assigned for vector 0xf9 [ 0.015475] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512 [ 0.015475] Last level dTLB entri...

...Initializing cgroup subsys memory [ 5.294547] Initializing cgroup subsys devices [ 5.294551] Initializing cgroup subsys freezer [ 5.294554] Initializing cgroup subsys net_cls [ 5.294558] Initializing cgroup subsys blkio [ 5.294561] Initializing cgroup subsys perf_event [ 5.294619] tseg: 00bd800000 [ 5.294623] CPU: Physical Processor ID: 0 [ 5.294625] CPU: Processor Core ID: 0 [ 5.294628] mce: CPU supports 2 MCE banks [ 5.294644] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512 [ 5.294644] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 512 [ 5.294644] tlb_fl...