Displaying 10 results from an estimated 10 matches for "tobool5".
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tobool
2010 Dec 17
0
[LLVMdev] Branch delay slots broken.
...ction:
; ModuleID = '../../../src/c/string/memset.c'
target datalayout =
"E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-n32"
target triple = "mips-ellcc-unknown"
define i8* @memset(i8* %m, i32 %c, i32 %n) nounwind {
entry:
%tobool5 = icmp eq i32 %n, 0
br i1 %tobool5, label %while.end, label %bb.nph
bb.nph: ; preds = %entry
%conv = trunc i32 %c to i8
br label %while.cond
while.cond: ; preds = %while.cond,
%bb.nph
%indvar = phi i32 [...
2010 Dec 17
2
[LLVMdev] Branch delay slots broken.
Hi Richard,
> You changes work for me also. I applied something similar to the Mips CG
> and they worked there also. Thanks again.
I can't reproduce the same problem here for Mips using clang, could
you please attach the bitcode you used?
Thanks
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
2010 Dec 18
2
[LLVMdev] Branch delay slots broken.
.../../src/c/string/memset.c'
> target datalayout =
> "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-n32"
> target triple = "mips-ellcc-unknown"
>
> define i8* @memset(i8* %m, i32 %c, i32 %n) nounwind {
> entry:
> %tobool5 = icmp eq i32 %n, 0
> br i1 %tobool5, label %while.end, label %bb.nph
>
> bb.nph: ; preds = %entry
> %conv = trunc i32 %c to i8
> br label %while.cond
>
> while.cond: ; preds = %while.cond,
>...
2019 Sep 30
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...%0, 1
> br label %if.end4
>
> if.end4: ; preds = %if.then2, %entry
> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
> %mul = mul nsw i32 %b.addr.0, %spec.select
> %tobool5 = icmp eq i16 %neg.1, 0
> %sub7 = sub nsw i32 0, %mul
> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
> ret i32 %spec.select18
> }
>
> attributes #0 = { norecurse nounwind optsize readnone "correctly-rounded-divide-sqrt-fp-math"="false" "d...
2019 Sep 29
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...i16 %0, 1
> br label %if.end4
>
> if.end4: ; preds = %if.then2, %entry
> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
> %mul = mul nsw i32 %b.addr.0, %a.addr.0
> %tobool5 = icmp eq i16 %neg.1, 0
> %sub7 = sub nsw i32 0, %mul
> %res.0 = select i1 %tobool5, i32 %mul, i32 %sub7
> ret i32 %res.0
> }
>
> The offending part here is this: %a.lobit = lshr i32 %a, 31 . Instead of just creating a “select” instruction, as the original code suggested wi...
2019 Sep 30
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...r i16 %0, 1
> br label %if.end4
>
> if.end4: ; preds = %if.then2,
> %entry
> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
> %mul = mul nsw i32 %b.addr.0, %spec.select
> %tobool5 = icmp eq i16 %neg.1, 0
> %sub7 = sub nsw i32 0, %mul
> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
> ret i32 %spec.select18
> }
>
> attributes #0 = { norecurse nounwind optsize readnone
> "correctly-rounded-divide-sqrt-fp-math"="false"
> &qu...
2019 Oct 01
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...gt;
>>> if.end4: ; preds = %if.then2, %entry
>>> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
>>> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
>>> %mul = mul nsw i32 %b.addr.0, %spec.select
>>> %tobool5 = icmp eq i16 %neg.1, 0
>>> %sub7 = sub nsw i32 0, %mul
>>> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
>>> ret i32 %spec.select18
>>> }
>>>
>>> attributes #0 = { norecurse nounwind optsize readnone "correctly-rounded-divide-s...
2019 Sep 25
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
Changing the order of the checks in CodeGenPrepare::optimizeSelectInst()
sounds good to me.
But you may need to go further for optimum performance. For example, we may
be canonicalizing math/logic IR patterns into 'select' such as in the
recent:
https://reviews.llvm.org/D67799
So if you want those to become ALU ops again rather than branches, then you
need to do the transform later in
2019 Oct 03
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...; if.end4: ; preds = %if.then2, %entry
>>>> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
>>>> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
>>>> %mul = mul nsw i32 %b.addr.0, %spec.select
>>>> %tobool5 = icmp eq i16 %neg.1, 0
>>>> %sub7 = sub nsw i32 0, %mul
>>>> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
>>>> ret i32 %spec.select18
>>>> }
>>>>
>>>> attributes #0 = { norecurse nounwind optsize readnone "co...
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...[13 x i16]* %y.i, i32 0, i32 8
store i16 %29, i16* %incdec.ptr1.6.i.i, align 2, !tbaa !5
%incdec.ptr1.8.i.i = getelementptr inbounds [13 x i16]* %y.i, i32 0, i32 9
store i16 %28, i16* %incdec.ptr1.7.i.i, align 2, !tbaa !5
%conv.i = zext i16 %3 to i32
%and.i256 = and i32 %conv.i, 32768
%tobool5.i = icmp eq i32 %and.i256, 0
br i1 %tobool5.i, label %if.end11.i, label %if.then6.i
if.then6.i: ; preds = %if.end.i257
%and9.i = and i32 %conv.i, 32767
%conv10.i = trunc i32 %and9.i to i16
br label %if.end11.i
if.end11.i:...