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Hi! before InstCombine (llvm::createInstructionCombiningPass()) I have a trunc from i8 to i1 and then a select: %45 = load i8* @myGlobal, align 1 %tobool = trunc i8 %45 to i1 %cond = select i1 %tobool, float 1.000000e+00, float -1.000000e+00 after instCombine I have: %29 = load i8* @myGlobal, align 1 %30 = and i8 %29, 1 %tobool = icmp ne i8 %30, 0 %cond = select i1 %tobool, float 1.000000e+00, float -1.000000e+00 is this a bug or intended? My ver...

Hi, The phase of instruction combine cannot handle the instruction %4 = select i1 %tobool.i, metadata !12, metadata !10 generated by the phase of CFG simplification and the compiler generates an assertion failure. I wonder whether this is valid LLVM IR: %4 = select i1 %tobool.i, metadata !12, metadata !10 Before CFGSimplify cond.true.i: ; preds =...

...l_insert_Ev(%struct.G* %this) local_unnamed_addr #0 comdat align 2 { entry: %call = call dereferenceable(16) %struct.G* @_ZN1G5finalEv(%struct.G* %this) %link_point_c.i = getelementptr inbounds %struct.G, %struct.G* %call, i64 0, i32 1 %0 = load i32, i32* %link_point_c.i, align 8, !tbaa !1 %tobool.i = icmp eq i32 %0, 0 %1 = bitcast %struct.G* %call to i8** %2 = load i8*, i8** %1, align 8, !tbaa !7 br i1 %tobool.i, label %cond.false.i, label %cond.true.i cond.true.i: ; preds = %entry %add.ptr.i = getelementptr inbounds i8, i8* %2, i64 8 %left_.i...

>> Hi! >> >> before InstCombine (llvm::createInstructionCombiningPass()) I have >> a trunc from i8 to i1 and then a select: >> >> %45 = load i8* @myGlobal, align 1 >> %tobool = trunc i8 %45 to i1 >> %cond = select i1 %tobool, float 1.000000e+00, float -1.000000e+00 >> >> after instCombine I have: >> >> %29 = load i8* @myGlobal, align 1 >> %30 = and i8 %29, 1 >> %tobool = icmp ne i8 %30, 0 >> %cond = select i1 %tobool, floa...

On Dec 27, 2011, at 5:09 AM, Jochen Wilhelmy wrote: > Hi! > > before InstCombine (llvm::createInstructionCombiningPass()) I have > a trunc from i8 to i1 and then a select: > > %45 = load i8* @myGlobal, align 1 > %tobool = trunc i8 %45 to i1 > %cond = select i1 %tobool, float 1.000000e+00, float -1.000000e+00 > > after instCombine I have: > > %29 = load i8* @myGlobal, align 1 > %30 = and i8 %29, 1 > %tobool = icmp ne i8 %30, 0 > %cond = select i1 %tobool, float 1.000000e+00, float -1.00000...

...rst element define void @f(i32* nocapture %l0) { entry: %fc_ = alloca [1 x i32] %f.b.v = load [1 x i32]* @f.b store [1 x i32] %f.b.v, [1 x i32]* %fc_ %0 = getelementptr [1 x i32]* %fc_, i64 0, i64 0 ; load the first element of the constant array, which is actually 1 %1 = load i32* %0 %tobool = icmp ne i32 %1, 0 ; check the first element to see if it is 1, which is actually always true since the first element of constant array is 1 br i1 %tobool, label %2, label %4 ; <label>:2 ; true branch store i32 1, i32* %l0; %3 = load i32* %l0; br label %4...

...%fc_ = alloca [1 x i32] >> %f.b.v = load [1 x i32]* @f.b >> store [1 x i32] %f.b.v, [1 x i32]* %fc_ >> %0 = getelementptr [1 x i32]* %fc_, i64 0, i64 0 ; load the first >> element of the constant array, which is actually 1 >> %1 = load i32* %0 >> %tobool = icmp ne i32 %1, 0 ; check the first element to >> see if it is 1, which is actually always true since the first element of >> constant array is 1 >> br i1 %tobool, label %2, label %4 >> >> ; <label>:2 ; true branch >> store...

...en Wilhelmy <j.wilhelmy at arcor.de>wrote: > > >> Hi! > >> > >> before InstCombine (llvm::createInstructionCombiningPass()) I have > >> a trunc from i8 to i1 and then a select: > >> > >> %45 = load i8* @myGlobal, align 1 > >> %tobool = trunc i8 %45 to i1 > >> %cond = select i1 %tobool, float 1.000000e+00, float -1.000000e+00 > >> > >> after instCombine I have: > >> > >> %29 = load i8* @myGlobal, align 1 > >> %30 = and i8 %29, 1 > >> %tobool = icmp ne i8 %30, 0 >...

...rget language >> that does not support conditional branches and in fact only supports >> structured control flow, eg. If and while. What's the difference between an "if" and a conditional branch? [bg] Consider the LLVM code: define i32 @foo(i32 %x, i32 %y) { entry: %tobool = icmp eq i32 %x, 0 ; <i1> [#uses=1] br i1 %tobool, label %ifelse, label %ifthen ifthen: ; preds = %entry %add = add i32 %x, 10 ; <i32> [#uses=1] ret i32 %add ifelse: ; preds = %entry %call = tail call i32 (...)* @bar( ) ; <i32>...

I decided to pump some IR through the optimizers and was surprised to find that we don't choose to canonicalize any of the following functions to the other even though they are all roughly the same. define i32 @f1(i32 %x, i32 %m) #0 { entry: %and = and i32 %m, 32896 %tobool = icmp ne i32 %and, 0 %cond = select i1 %tobool, i32 8, i32 0 %shr = lshr i32 %x, %cond ret i32 %shr } ; Function Attrs: nounwind readnone uwtable define i32 @f2(i32 %x, i32 %m) #0 { entry: %and = and i32 %m, 32896 %tobool = icmp eq i32 %and, 0 %shr = lshr i32 %x, 8 %x.shr = select i...

On Aug 11, 2008, at 2:02 PM, Benedict Gaster wrote: > We would like to develop a code generator using LLVM for a target > language that does not support conditional branches and in fact only > supports structured control flow, eg. If and while. What's the difference between an "if" and a conditional branch? > As far as I can tell that the problem with doing this in

...Let us take the following C program into consideration: ``` int calculateImportantResult(int a, int b) { int result = 0; if (a) { result = a + b; } return result; } ``` A straightforward lowering to LLVM IR could be: ``` define i32 @calculateImportantResult(i32 %a, i32 %b) { entry: %tobool = icmp ne i32 %a, 0 br i1 %tobool, label %if.then, label %if.end if.then: %add = add nsw i32 %a, %b br label %if.end if.end: %result = phi i32 [ %add, %if.then ], [ 0, %entry ] ret i32 %result } ``` Moving `%add` to the `%entry` block would be preferable and would allow further optimiz...

We would like to develop a code generator using LLVM for a target language that does not support conditional branches and in fact only supports structured control flow, eg. If and while. As far as I can tell that the problem with doing this in LLVM today, is that it does not support these high-level constructs and instead all control flow is implemented as branches. It is ³fairly²

...++c; } while (*c); } And in IR form: define void @test(i8* nocapture %c) { entry: %.pre = load i8* %c, align 1 br label %do.body do.body: %0 = phi i8 [ %.pre, %entry ], [ %1, %if.end ] %c.addr.0 = phi i8* [ %c, %entry ], [ %incdec.ptr, %if.end ] %tobool = icmp eq i8 %0, 0 br i1 %tobool, label %do.end, label %if.end if.end: %incdec.ptr = getelementptr inbounds i8* %c.addr.0, i64 1 %1 = load i8* %incdec.ptr, align 1 %tobool1 = icmp eq i8 %1, 0 br i1 %tobool1, label %do.end, label %do.body do.end: ret void...

On Aug 12, 2008, at 2:39 AM, Benedict Gaster wrote: > [bg] Consider the LLVM code: > > define i32 @foo(i32 %x, i32 %y) { > entry: > %tobool = icmp eq i32 %x, 0 ; <i1> [#uses=1] > br i1 %tobool, label %ifelse, label %ifthen > > ifthen: ; preds = %entry > %add = add i32 %x, 10 ; <i32> [#uses=1] > ret i32 %add > > ifelse: ; preds = %entry > %call = tail call i...

...2, align 4 %c = alloca i32, align 4 %e = alloca i32, align 4 ; 1 = MemoryDef(liveOnEntry) store i32* %b, i32** %b.addr, align 8 ; 2 = MemoryDef(1) store i32 0, i32* %a, align 4 ; 3 = MemoryDef(2) store i32 12, i32* %d, align 4 ; MemoryUse(1) %0 = load i32*, i32** %b.addr, align 8 %tobool = icmp ne i32* %0, null br i1 %tobool, label %if.then, label %if.end if.then: ; preds = %entry ; 4 = MemoryDef(3) store i32 42, i32* %a, align 4 ; 5 = MemoryDef(4) store i32 32, i32* %d, align 4 br label %if.end if.end:...

...x1; } int arg; int main (void) { int x1 = foo(arg); printf("%x\n", x1); return 0; } This program has no UB and it should print "1'. Clang at -O2 turns foo() into this: define i32 @foo(i32 %x0) #0 { entry: %shr = ashr i32 %x0, 27 %sub = add nsw i32 %shr, -27 %tobool = icmp ne i32 %sub, 0 %shr1 = lshr i32 1, %sub %cond = select i1 %tobool, i32 %sub, i32 %shr1 %cmp = icmp ne i32 %cond, 0 %conv = zext i1 %cmp to i32 ret i32 %conv } Although the translation is very straightforward, there's a problem: %shr1 is a poison value and although it is...

On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would

...int result = 0; > if (a) { > result = a + b; > } > return result; > } > ``` > > A straightforward lowering to LLVM IR could be: > ``` > define i32 @calculateImportantResult(i32 %a, i32 %b) { > entry: > %tobool = icmp ne i32 %a, 0 > br i1 %tobool, label %if.then, label %if.end > > if.then: > %add = add nsw i32 %a, %b > br label %if.end > > if.end: > %result = phi i32 [ %add, %if.then ], [ 0, %entry ] > ret i32 %result > } > ```...

...asm volatile ("" : : : "cc") constraint. The LLVM IR has the what appears to be an appropriate inline ASM directive: --- entry: tail call void @foo() #2 %0 = load i32* @a, align 4, !tbaa !1 %sub = add nsw i32 %0, -1 store i32 %sub, i32* @a, align 4, !tbaa !1 %tobool = icmp eq i32 %sub, 0 tail call void asm sideeffect "", "~{cc},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !5 tail call void @foo() #2 br i1 %tobool, label %if.end, label %return if.end: ; preds = %entry tail call void @foo(...