search for: t8

...elation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0, Register:i64 %vreg1, t4 t15: ch = CopyToReg t0, Register:i64 %vreg2, t8 t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t8:1 t...

...acros and I need to make sure, at this time at least, that the individual instructions are not reordered or moved around. There are dependencies sometimes between the instructions that I'm not sure how to tell LLVM about. For example, this first one is a two instruction macro where register T8 is implicitly set by the first instruction and used by the second instruction. T8 is not a mips16 registers but some instructions use it implicitly and it can function as a condition code register. In this first case, I do a compare (CMP) and the result sets T8 and then the branch instruction...

...7: $(OBJ)/t7.out - set -xe ; if ${TEST_SSH_SSH} -Q key | grep -q ^ssh-dss ; then \ + set -xe ; if ${TEST_SSH_SSH} -Q key | grep -q "^ssh-dss" ; then \ ${TEST_SSH_SSHKEYGEN} -lf $(OBJ)/t7.out > /dev/null ; \ ${TEST_SSH_SSHKEYGEN} -Bf $(OBJ)/t7.out > /dev/null ; \ fi $(OBJ)/t8.out: - set -xe ; if ssh -Q key | grep -q ^ssh-dss ; then \ + set -xe ; if ssh -Q key | grep -q "^ssh-dss" ; then \ ${TEST_SSH_SSHKEYGEN} -q -t dsa -N '' -f $@ ; \ fi t8: $(OBJ)/t8.out - set -xe ; if ssh -Q key | grep -q ^ssh-dss ; then \ + set -xe ; if ssh -Q key | grep -q...

...gt; least, that the individual instructions are not reordered or moved around. >> >> There are dependencies sometimes between the instructions that I'm not >> sure how to tell LLVM about. >> >> For example, this first one is a two instruction macro where register T8 >> is implicitly set by the first instruction and used by the second >> instruction. >> >> T8 is not a mips16 registers but some instructions use it implicitly and >> it can function as >> a condition code register. >> >> In this first case, I do a...

...ure, at this time at > least, that the individual instructions are not reordered or moved around. > > There are dependencies sometimes between the instructions that I'm not > sure how to tell LLVM about. > > For example, this first one is a two instruction macro where register T8 > is implicitly set by the first instruction and used by the second > instruction. > > T8 is not a mips16 registers but some instructions use it implicitly and > it can function as > a condition code register. > > In this first case, I do a compare (CMP) and the result sets...

i'm trying to formulate the optimal way to do comparison testing for mips 16. on mips32 there are no condition codes. you can test a<b and place the result in a register in mip32. on mips16 you can do the same, however, the register is always T8==24. T8 is not directly accessible by most mips16 instructions, but can be directly moved to a generally accessible mips16 register, and can also used in tests for a conditional branch. later you can conditionally branch based on this register it's possible for me to make a pseudo instruct...

int %nlz10(uint %param.x) { %.t3 = shr uint %param.x, ubyte 1 ; <uint> [#uses=1] %.t4 = or uint %.t3, %param.x ; <uint> [#uses=2] %.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1] %.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2] %.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1] %.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2] %.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1] %.t16 = or u...

...\n" + "addiu $29, $29, -64\n" ".cprestore 16\n" // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain @@ -115,35 +115,35 @@ // concerned. We also need to save the ra register since it contains the // original return address, and t8 register since it contains the address // of the end of function stub. - "sw $a0, 20($sp)\n" - "sw $a1, 24($sp)\n" - "sw $a2, 28($sp)\n" - "sw $a3, 32($sp)\n" - "sw $ra, 36($sp)\n" - "sw $t8, 40($sp)\n" - "sd...

...e individual instructions are not reordered or moved around. >>> >>> There are dependencies sometimes between the instructions that I'm not >>> sure how to tell LLVM about. >>> >>> For example, this first one is a two instruction macro where register T8 >>> is implicitly set by the first instruction and used by the second >>> instruction. >>> >>> T8 is not a mips16 registers but some instructions use it implicitly and >>> it can function as >>> a condition code register. >>> >>&g...

...ons are not reordered or moved around. >>>> >>>> There are dependencies sometimes between the instructions that I'm not >>>> sure how to tell LLVM about. >>>> >>>> For example, this first one is a two instruction macro where register T8 >>>> is implicitly set by the first instruction and used by the second >>>> instruction. >>>> >>>> T8 is not a mips16 registers but some instructions use it implicitly and >>>> it can function as >>>> a condition code register...

...%cmp7 = xor i1 %1, %cmp6 ... and the SelectionDAG before TypeLegalizer is like this. t0: ch = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t...

After discussions last night, I'm leaning towards going legit with all my pseudo expansions in Mips 16. Some I think I can clearly do by just putting in the proper side effects of implicit registers (T8 the condition code register as used by mips 16). But I'm still left with some pseudos that have jmp .+4 type instructions in them. The original Mips port was to Mips I and Mips I, like Mips 16, has no conditional store instructions. There was some super ugly code there to do a test and the...

...nDAG has 44 nodes: t11: i16 = Constant<0> t0: ch = EntryToken t3: ch = llvm.clp.set.rspa t0, TargetConstant:i16<392>, Constant:i32<64> t5: ch = llvm.clp.set.rspb t3, TargetConstant:i16<393>, Constant:i32<64> t8: ch = llvm.clp.set.rspsu t5, TargetConstant:i16<394>, Constant:i32<8> t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 t16: ch = store<Volatile ST4[@x2](tbaa=&lt...

...in it, and all will work more or less? I'm trying to take the next step now and separate out the blobs that I'm emitted as part of pseudos. I want to have individual instructions, even if they are part of bundles. That also makes it easier on the direct object emitter. MOdelling this T8 register (the source of most of the pseudos) as an unallocatable condition code regiter it probably the right thing to do. I will think about that. This particular register can be copied to normal mips16 registers but I try and avoid that and instead use it as is using special instructions that i...

...t<0> > >                   t0: ch = EntryToken > >                 t3: ch = llvm.clp.set.rspa t0, TargetConstant:i16<392>, > Constant:i32<64> > > t5: ch = llvm.clp.set.rspb t3, TargetConstant:i16<393>, Constant:i32<64> > >             t8: ch = llvm.clp.set.rspsu t5, TargetConstant:i16<394>, > Constant:i32<8> > >           t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 > >         t16: ch =...

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

...umns, to which I found a solution but it doesn't feel to be a smart solution, any ideas or help of how to improve this would be welcomed. # sample code: # creating a simple file zz <- file("ex.data", "w") # open an output file connection cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep = "\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep = "\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep = "\n") (temp.file = scan("ex.data", what = "&quot...

...s converted into this by llc: Creating new node: t2: i16,ch = CopyFromReg t0, Register:i16 %3 Creating new node: t4: i16,ch = CopyFromReg t0, Register:i16 %0 Creating new node: t5: i16 = add t2, t4 Creating constant: t6: i16 = Constant<0> Creating new node: t7: i16 = undef Creating new node: t8: i8,ch = load<(load 1 from %ir.scevgep1, !tbaa !2)> t0, t5, undef:i16 Creating new node: t10: i16,ch = CopyFromReg t0, Register:i16 %2 Creating new node: t11: i16 = add t10, t4 Creating new node: t12: ch = store<(store 1 into %ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16 Creating con...

I'm looking at the instruction formats and I can't grok the comments. For example: // SSSE3 Instruction Templates: // // SS38I - SSSE3 instructions with T8 prefix. // SS3AI - SSSE3 instructions with TA prefix. // Where are these prefix names coming from? I can't find any mention of them in the Intel literature. Also, there's this curious table: // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that...

...tle guidance. Here's the data I am trying to fit: ------------------------------------ > myPbmcData Grouped Data: lnCount ~ Time | Type Time Mouse Count Type lnCount 1 0 T0-1 37.6 Naive 3.627004 2 0 T0-2 23.6 Naive 3.161247 3 0 T0-3 49.2 Naive 3.895894 4 8 T8-1 20.8 Naive 3.034953 5 8 T8-2 26.9 Naive 3.292126 6 8 T8-3 34.0 Naive 3.526361 7 24 T24-1 36.8 Naive 3.605498 8 24 T24-2 34.0 Naive 3.526361 9 24 T24-3 19.6 Naive 2.975530 10 48 T48-1 55.4 Naive 4.014580 11 48 T48-2 54.2 Naive 3.992681 12 48 T48-3 51.4 Na...