search for: st8

Displaying 20 results from an estimated 81 matches for "st8".

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2008 Mar 28
0
[08/17][PATCH] kvm/ia64: Add interruption vector table for vmm.
...; >+ invala /* M */ >+ mov r30=cr.ifs >+ ;; >+ addl r1=-VMM_PT_REGS_SIZE,r1 >+ ;; >+ adds r17=2*L1_CACHE_BYTES,r1 /* really: biggest cache-line >size */ >+ adds r16=PT(CR_IPSR),r1 >+ ;; >+ lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES >+ st8 [r16]=r29 /* save cr.ipsr */ >+ ;; >+ lfetch.fault.excl.nt1 [r17] >+ mov r29=b0 >+ ;; >+ adds r16=PT(R8),r1 /* initialize first base pointer */ >+ adds r17=PT(R9),r1 /* initialize second base pointer */ >+ mov r18=r0 /* make sure r18 isn't...
2008 Mar 28
0
[08/17][PATCH] kvm/ia64: Add interruption vector table for vmm.
...; >+ invala /* M */ >+ mov r30=cr.ifs >+ ;; >+ addl r1=-VMM_PT_REGS_SIZE,r1 >+ ;; >+ adds r17=2*L1_CACHE_BYTES,r1 /* really: biggest cache-line >size */ >+ adds r16=PT(CR_IPSR),r1 >+ ;; >+ lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES >+ st8 [r16]=r29 /* save cr.ipsr */ >+ ;; >+ lfetch.fault.excl.nt1 [r17] >+ mov r29=b0 >+ ;; >+ adds r16=PT(R8),r1 /* initialize first base pointer */ >+ adds r17=PT(R9),r1 /* initialize second base pointer */ >+ mov r18=r0 /* make sure r18 isn't...
2008 Jul 17
0
[PATCH 17/29] ia64/pv_ops/xen: define xen paravirtualized instructions for hand written assembly code
...(\pred) mov \reg = r8 + .exitm + .endif + + (\pred) mov \clob = r8 + (\pred) XEN_HYPER_GET_PSR + ;; + (\pred) mov \reg = r8 + (\pred) mov r8 = \clob +.endm +#define MOV_FROM_PSR(pred, reg, clob) __MOV_FROM_PSR pred, reg, clob + + +#define MOV_TO_IFA(reg, clob) \ + movl clob = XSI_IFA; \ + ;; \ + st8 [clob] = reg \ + +#define MOV_TO_ITIR(pred, reg, clob) \ +(pred) movl clob = XSI_ITIR; \ + ;; \ +(pred) st8 [clob] = reg + +#define MOV_TO_IHA(pred, reg, clob) \ +(pred) movl clob = XSI_IHA; \ + ;; \ +(pred) st8 [clob] = reg + +#define MOV_TO_IPSR(pred, reg, clob) \ +(pred) movl clob = XSI_...
2013 Feb 08
2
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1 %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2 MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112 %vreg190<def> = MOVSDrm <fi#0&...
2013 Feb 08
0
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...gt;, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1 > %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2 > MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 > %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 > %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112 > %vreg190<def> =...
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested
2013 Aug 02
0
[LLVMdev] Missing optimization - constant parameter
...y 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg, <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg1 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2; mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2 96B %RDI<def> = COPY %vreg2; GR64:...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
For the little C test program where a constant is stored in memory and also used as a parameter: #include <stdint.h> uint64_t val, *p; extern uint64_t xtr( uint64_t); uint64_t caller() { uint64_t x; p = &val; x = 12345123400L; *p = x; return xtr(x); } clang (3.2, 3.3 and svn) generates the following X86 code (at -O3): caller: movq
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...%vreg5<def> = ADDIStocHA %X2, <ga:@A>; G8RC_and_G8RC_NOX0:%vreg5 480B %vreg6<def> = LDtocL <ga:@A>, %vreg5, %X2<imp-use>; mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg6,%vreg5 504B %X3<def> = LI8 0 512B STD %vreg4, 0, %vreg6; mem:ST8[getelementptr inbounds ([100 x i64], [100 x i64]* @A, i64 0, i64 0)](tbaa=!4) G8RC:%vreg4 G8RC_and_G8RC_NOX0:%vreg6 520B STD %vreg9, 8, %vreg6; mem:ST8[getelementptr inbounds ([100 x i64], [100 x i64]* @A, i64 0, i64 1)](tbaa=!4) G8RC:%vreg9 G8RC_and_G8RC_NOX0:%vreg6 528B...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
...lt;def> = MOV64rm %RIP, 1, %noreg, > <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 > 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], > %noreg; mem:LD8[GOT] GR64:%vreg1 > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; > mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2 > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2; > mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2 > 96B %RDI<def>...
2006 Jun 26
0
[klibc 25/43] ia64 support for klibc
...r2 = ar.bsp // save backing store pointer + mov r3 = pr // save predicates + flushrs + ;; + // + // save user Unat register + // + mov r16 = ar.lc // save loop count register + mov r14 = ar.unat // save user Unat register + + st8 [r10] = r3, J_LC-J_PREDS + st8 [r11] = r2, J_R4-J_BSP + ;; + st8 [r10] = r16, J_R5-J_LC + st8 [r32] = r14, J_NATS // Note: Unat at the + // beginning of the save area + mov r15 = ar.pfs + ;; + // + // save preserved general...
2008 Feb 26
8
[PATCH 0/8] RFC: ia64/xen TAKE 2: paravirtualization of hand written assembly code
Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place
2008 Feb 26
8
[PATCH 0/8] RFC: ia64/xen TAKE 2: paravirtualization of hand written assembly code
Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place
2008 May 19
20
[PATCH 00/23] ia64/xen domU take 6
Hi. This patchset implements ia64/xen domU support based on ia64/pv_ops frame work which was sent as another patchest. Changes from take 5 are rebased to Linux 2.6.26-rc3, bug fix ivt.S paravirtualization and multi entry point support. I believe these patches can be applied to the linux ia64 repository. This patchset does the followings. - Some preparation work. Mainly importing header files to
2008 May 19
20
[PATCH 00/23] ia64/xen domU take 6
Hi. This patchset implements ia64/xen domU support based on ia64/pv_ops frame work which was sent as another patchest. Changes from take 5 are rebased to Linux 2.6.26-rc3, bug fix ivt.S paravirtualization and multi entry point support. I believe these patches can be applied to the linux ia64 repository. This patchset does the followings. - Some preparation work. Mainly importing header files to
2013 Feb 04
2
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
...for which I want to regenerate the bundle header (You see that %R17 is not currently in the def list for the bundle header). v BUNDLE %P3<imp-def>, %R29<imp-use>, %D8<imp-use,kill>, %D9<imp-use,kill>, %R6<imp-use> *^v STrid_indexed %R29, 80, %D8<kill>; mem:ST8[FixedStack2] *^v STrid_indexed %R29, 72, %D9<kill>; mem:ST8[FixedStack3] *^v %P3<def> = CMPEQri %R6, 0 *^ %R17<def> = TFR_cdnNotPt %P3<internal>, %R1 v BUNDLE %R29<imp-use>, %D10<imp-use,kill>, %R7<imp-use>, %D6<imp-use> (next bundle). finaliz...
2013 Feb 04
0
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
...e > bundle header (You see that %R17 is not currently in the def list for the > bundle header). > > > v BUNDLE %P3<imp-def>, %R29<imp-use>, %D8<imp-use,kill>, > %D9<imp-use,kill>, %R6<imp-use> > *^v STrid_indexed %R29, 80, %D8<kill>; mem:ST8[FixedStack2] > *^v STrid_indexed %R29, 72, %D9<kill>; mem:ST8[FixedStack3] > *^v %P3<def> = CMPEQri %R6, 0 > *^ %R17<def> = TFR_cdnNotPt %P3<internal>, %R1 > v BUNDLE %R29<imp-use>, %D10<imp-use,kill>, %R7<imp-use>, %D6<imp-use> >...
2013 Aug 05
0
[LLVMdev] Missing optimization - constant parameter
..., 1, %noreg, > > <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 > > 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], > > %noreg; mem:LD8[GOT] GR64:%vreg1 > > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; > > mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 > > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2 > > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2; > > mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2 > > 96B...
2008 Apr 30
23
[PATCH 00/23] ia64/xen domU take 5
Hi. This patchset implements ia64/xen domU support based on ia64/pv_ops frame work which was sent as another patchest. This patchset does the followings. - Some preparation work. Mainly importing header files to define related structures. - Then, define functions related to hypercall which is the way to communicate with Xen hypervisor. - Add some helper functions which is necessary to