search for: t23

Holger Wansing <linux at wansing-online.de> writes: > I found, that this not only a problem of the netinst cd, but > also hardware dependent. > I can boot my old 486 Toshiba Satellite laptop with this cd, > but on my IBM Thinkpad T23 the cd produces the isolinux error: > > Error: no configuration file found. > > (The T23 does not contain the original optical drive, I changed the drive > myself years ago to an NEC ND-7551A. I had no problems in the past years > with this drive). > > I checked the md5sum...

...lt;Volatile ST4[@x3](tbaa=<0x3dbe418>)> t16, ConstantFP:f32<3.000000e+00>, GlobalAddress:i16<float* @x3> 0, undef:i16 t22: ch = store<Volatile ST4[@x4](tbaa=<0x3dbe418>)> t19, ConstantFP:f32<4.000000e+00>, GlobalAddress:i16<float* @x4> 0, undef:i16 t23: f32,ch = load<Volatile LD4[@x1](tbaa=<0x3dbe418>)> t22, GlobalAddress:i16<float* @x1> 0, undef:i16 t24: f32,ch = load<Volatile LD4[@x2](tbaa=<0x3dbe418>)> t23:1, GlobalAddress:i16<float* @x2> 0, undef:i16 t25: f32,ch = load<Volatile LD4[@x3](tbaa=<0x3d...

...ter:i32 %vreg79 t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 t20: i32 = AssertZext t18, ValueType:ch:i1 t23: i1 = setcc t20, Constant:i32<0>, seteq:ch t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396 t28: i1 = setcc t25, Constant:i32<255>, setugt:ch t29: i1 = and t23, t28 t37: i1 = setcc t29, Constant:i1<-1>, setne:ch t33: ch = brcond t16, t37,...

...= CopyFromReg t0, Register:i32 %vreg1 >> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 >> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 >> t20: i32 = AssertZext t18, ValueType:ch:i1 >> t23: i1 = setcc t20, Constant:i32<0>, seteq:ch >> t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396 >> t28: i1 = setcc t25, Constant:i32<255>, setugt:ch >> t29: i1 = and t23, t28 >> t37: i1 = setcc t29, Constant:i1<-1>, set...

...dbe418>)> t16, > ConstantFP:f32<3.000000e+00>, GlobalAddress:i16<float* @x3> 0, undef:i16 > >     t22: ch = store<Volatile ST4[@x4](tbaa=<0x3dbe418>)> t19, > ConstantFP:f32<4.000000e+00>, GlobalAddress:i16<float* @x4> 0, undef:i16 > > t23: f32,ch = load<Volatile LD4[@x1](tbaa=<0x3dbe418>)> t22, > GlobalAddress:i16<float* @x1> 0, undef:i16 > >   t24: f32,ch = load<Volatile LD4[@x2](tbaa=<0x3dbe418>)> t23:1, > GlobalAddress:i16<float* @x2> 0, undef:i16 > >   t25: f32,ch = loa...

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

...int* ba1) { ba1[0] *= ba1[2] + 2; } > > void main_b( int* inB) { void (*func)(int*) = Bye; func(inB+1); } > > > > --------- cmd sequence ------- > > $ clang++ -c -emit-llvm t1.cpp -o t1.bc > > $ clang++ -c -emit-llvm t1.cpp -o t2.bc > > $ llvm-link t1.bc t2.bc -o t23.bc > > $ clang -c t23.bc > > $ nm t23.o > > > > t1.o and t2.o have the same named function “_ZL3ByePi”. In order to > distinguish them, > > one gets a ‘1’ appended to it, making it “_ZL3ByePi1”. > > > > While the code is all correct, the problem is that...

...gt; t16, > ConstantFP:f32<3.000000e+00>, GlobalAddress:i16<float* @x3> 0, > undef:i16 > >     t22: ch = store<Volatile ST4[@x4](tbaa=<0x3dbe418>)> t19, > ConstantFP:f32<4.000000e+00>, GlobalAddress:i16<float* @x4> 0, > undef:i16 > > t23: f32,ch = load<Volatile LD4[@x1](tbaa=<0x3dbe418>)> t22, > GlobalAddress:i16<float* @x1> 0, undef:i16 > >   t24: f32,ch = load<Volatile LD4[@x2](tbaa=<0x3dbe418>)> t23:1, > GlobalAddress:i16<float* @x2> 0, undef:i16 > >   t25: f32,ch = load&...

...treatments with different time points. So, I used the following code to plot the boxplot and also to do anova. T11 <- c(280, 336, 249, 277, 429) T12 <- c(400, 397, 285, 407, 313) T13 <- c(725, 373, 364, 706, 249) T21 <- c(589, 257, 466, 248, 913) T22 <- c(519, 424, 512, 298, 907) T23 <- c(529, 479, 634, 354, 1015) obs <- c(T11, T12, T13, T21, T22, T23) treat <- c(rep("T1",15), rep("T2",15)) time <- c(rep("one",5), rep("two",5), rep("thr",5), rep("one",5), rep("two",5), rep("thr&q...

...>, Constant:i64<7> t16: v8i64 = add t7, t15 t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16 t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5 t22: i64 = AssertSext t20, ValueType:ch:i8 t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0> t24: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t23, undef:v8i64 t32: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<-1>, Constant:i64<-2>, Constant:i64<-3>, Cons...

It would be nice to have something like stata's outreg that lets regression output go into a form like Specification (1) Specification (2) Var 1 coef(1,1) coef(1,2) se(1,1) se(1,2) Var 2 coef(2,1) coef(2,2) se(2,1) se(2,2) I don't think this can be done in xtable? Thomas Davidoff Assistant Professor Haas School of Business UC Berkeley Berkeley, CA 94618 Phone: (510)

...e of 8 (like i1, or <4 x i1>, the result is undefined unless the unused bits are zero. You can see this in the debug output from llc: SelectionDAG has 15 nodes: t0: ch = EntryToken t21: i32 = X86ISD::KORTEST t19, t19 t22: i8 = X86ISD::SETCC Constant:i8<4>, t21 t23: i32 = zero_extend t22 t14: ch,glue = CopyToReg t0, Register:i32 %EAX, t23 t24: i16,ch = load<LD1[%XXX](align=4)(dereferenceable), zext from i8> t0, FrameIndex:i64<0>, undef:i64 t26: i16 = AssertZext t24, ValueType:ch:i4 t19: v16i1 = bitcast t26 t15: ch = X86ISD::R...

...6M/30G/56K/100M/12.1"XGA/1394/8XDVD+RW/1.6KG/ËÍ;µ××ù) 7500Ôª GR3/F (P3M1G/256M/40G/DVD+RW/14.1"TFT/56K/100M/2.5KG/NOFDD) 6100Ôª GR5/F (P3M1.13G/40G/256M/DVD+RW/14.1"TFT/56K/100M/2.5KG/NOFDD) 7500Ôª 3.IBM A31-H5A(PIV1.6G/256M/60G/15.1"TFT/56K/DVDRW,FDD/10-100MÎÞÏßÍø¿¨3KG)18800Ôª T23-2TA/I73 (P3 1G/128M/20G/14.1"TFT/56K/DVD,FDD/10-1000M2.4KG)8750Ôª T23-8NA (P3 1.13G/128M/30G/14.1"TFT/56K/DVDFDD/10-100Íø¿¨2.4KG) 9400Ôª T23-9JA(P31.2G/128M/40G/14.1"TFT(1400*1050)/56K/DVDRWFDD(1kg)10-100m)13200Ôª T23-9RA(P31.2G/256M/60G/14.1"TFT(1400*1050)/56K/DVDRWFDD(1kg)10-...

...c(inB); } --------------- t2.cpp --------- static void Bye(int* ba1) { ba1[0] *= ba1[2] + 2; } void main_b( int* inB) { void (*func)(int*) = Bye; func(inB+1); } --------- cmd sequence ------- $ clang++ -c -emit-llvm t1.cpp -o t1.bc $ clang++ -c -emit-llvm t1.cpp -o t2.bc $ llvm-link t1.bc t2.bc -o t23.bc $ clang -c t23.bc $ nm t23.o t1.o and t2.o have the same named function “_ZL3ByePi”. In order to distinguish them, one gets a ‘1’ appended to it, making it “_ZL3ByePi1”. While the code is all correct, the problem is that this modified name cannot be demangled. That is what I am trying to fix...

...t-llvm -S failing.c -o failing.ll ) I reran passing -debug to llc to see what's happening at various stages of DAG optimization: clang -O0 -mllvm -debug -S failing.c -o failing.s The initial selection DAG has the AND op node: t22: i8 = srl t19, Constant:i64<1> * t23: i8 = and t22, Constant:i8<1>* t24: i32 = zero_extend t23 t27: i1 = setcc t24, Constant:i32<1>, seteq:ch t29: i1 = xor t27, Constant:i1<-1> t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48> t33: ch = br t31, BasicBlock:ch<if.then 0x...

...reran passing -debug to llc to see what's happening at various > stages of DAG optimization: > > clang -O0 -mllvm -debug -S failing.c -o failing.s > > The initial selection DAG has the AND op node: > > t22: i8 = srl t19, Constant:i64<1> > * t23: i8 = and t22, Constant:i8<1>* > t24: i32 = zero_extend t23 > t27: i1 = setcc t24, Constant:i32<1>, seteq:ch > t29: i1 = xor t27, Constant:i1<-1> > t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48> > t33: ch = br t31, Ba...

Dear colleagues, After installing Wine 0.9.30 (...mdk from winehq) on my Mandrake 10.1/ IBM T23 laptop, I tried "wine notepad" and various other variants of the same, nothing coming out. It has been able to find most of the libraries, after a lot of ENOTTY according to 'strace' (500K of output, so I didn't attached it here), but simply stucked, stopped to search for any...

I have the following selection DAG: SelectionDAG has 9 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15

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SYSLINUX 4.00 2010-06-28 EDD Load error - Boot error Booting from USB on old IBM T43 or newer Esprimo E5731E. No problems with version 3.86 and same usb-stick.