search for: sundeepk

...e above, as well as the simpler ones. I can't commit myself however to when that will be ready, so I'm just sharing what I've found out, maybe it's helpful. I'd be interested to hear your thoughts / approach in greater detail. Thanks! --Charlie. On 21 July 2015 at 06:10, <sundeepk at codeaurora.org> wrote: > typo corrected > > lcl_var = gbl_var; > for () { > ...access lcl_var... > } > gbl_var = lcl_var; > > >> Hello all, >> >> I am writing to get some feedback on an optimization that I would like to >> upstre...

...e no labels) for scheduling including terminators. 5. Control edge will make sure that terminator instruction is not reordered. Please let me know what you guys think. Thanks, Sundeep > -----Original Message----- > From: Das Gupta, Anshu > Sent: Thursday, March 29, 2012 1:46 PM > To: sundeepk at codeauroraforum.org; Kushwaha, Sundeep > Subject: FW: [LLVMdev] VLIWPacketizerList: failing to schedule terminators > > > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: Thu...

Hi All, I noticed LLVM target independent side is converting an ordered less than "setolt" into unordered greater than "setuge" operation. There are no target hooks to control going from the ordered mode into unordered. I am trying to figure out the best way to support unordered operation on Hexagon. We don't have a single instruction to do unordered operation. So we

On Tue, Jul 9, 2013 at 3:00 PM, <sundeepk at codeaurora.org> wrote: > Hi All, > > I noticed LLVM target independent side is converting an ordered less than > "setolt" into unordered greater than "setuge" operation. There are no > target hooks to control going from the ordered mode into unordered. >...

> The function ISD::getSetCCInverse() would probably be useful for you > here: you can use it to transform an unordered operation into an > ordered operation. Thanks for your reply Eli. I will check how to convert unordered operations back to ordered one. I have another related question - is it possible for frontend (clang) to generate unordered operation from the source code? -Sundeep

Hello all, I am writing to get some feedback on an optimization that I would like to upstream. The basic idea is to localize global variables inside loops so that it can be allocated into registers. For example, transform the following sequence static int gbl_var; void foo() { for () { ...access gbl_var... } } into something like static int gbl_var; void foo() { int lcl_var;

Hi all, I am analyzing auto inc/dec optimization on ARM. On some loops, I noticed aggressive post increment is resulting in poor code due to increased register pressure. I was wondering if there is a way to estimate register pressure during DAG Combiner. I am trying to come up with some heuristic based on # of DAG nodes, # of live ins and live outs, # of machine registers etc. Any suggestions?

Hi All, I am working on a bug in clang. I already have a fix for it and I am going through the "LLVM Testing Infrastructure Guide" to make sure I haven't broken anything else. I have few questions regarding the test suite infrastructure that I hope someone can answer. 1. I checked out and built llvm, clang, and test-suite from svn tip. When I run llvm/test *without* my changes on

> > 1. I checked out and built llvm, clang, and test-suite from svn tip. > When I > > run llvm/test *without* my changes on x86, I see 3 failures. Is it > expected? > > I was expecting svn tip on x86 to be clean. Is there a nightly > regression > > result available somewhere that I can check for broken tests. Here is > the > > report from my log: > >