llvm dev - Nov 2011 - [LLVMdev] Post increment and register pressure

Hi all,

I am analyzing auto inc/dec optimization on ARM. On some loops, I noticed
aggressive post increment is resulting in poor code due to increased
register pressure.

I was wondering if there is a way to estimate register pressure during DAG
Combiner. I am trying to come up with some heuristic based on # of DAG
nodes, # of live ins and live outs, # of machine registers etc. Any
suggestions?

Thanks.

-Sundeep

On Nov 7, 2011, at 8:51 AM, Sundeep wrote:
> Hi all,
> 
> I am analyzing auto inc/dec optimization on ARM. On some loops, I noticed
> aggressive post increment is resulting in poor code due to increased
> register pressure.
> 
> I was wondering if there is a way to estimate register pressure during DAG
> Combiner. I am trying to come up with some heuristic based on # of DAG
> nodes, # of live ins and live outs, # of machine registers etc. Any
> suggestions?
You really can't accurately estimate register pressure at this stage.

Evan
> 
> Thanks.
> 
> -Sundeep
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev