Displaying 20 results from an estimated 32 matches for "subc_3d".
2015 Mar 21
0
[PATCH] use defined method names where available
..._exa.c | 2 +-
10 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/src/nv10_exa.c b/src/nv10_exa.c
index 78bc739..7daa281 100644
--- a/src/nv10_exa.c
+++ b/src/nv10_exa.c
@@ -697,9 +697,9 @@ NVAccelInitNV10TCL(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0);
}
- BEGIN_NV04(push, SUBC_3D(0x290), 1);
+ BEGIN_NV04(push, NV10_3D(UNK0290), 1);
PUSH_DATA (push, (0x10<<16)|1);
- BEGIN_NV04(push, SUBC_3D(0x3f4), 1);
+ BEGIN_NV04(push, NV10_3D(UNK03F4), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV04_GRAPH(3D, NOP), 1);
@@ -707,12 +707,12 @@ NVAccelInitNV10TCL(ScrnInfoPtr pScr...
2016 Oct 16
0
[PATCH 2/5] nvc0: make use of the new hwdefs for TEX_CB_INDEX
...it a/src/nvc0_accel.c b/src/nvc0_accel.c
index 52a17db..0682806 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0x00000001);
BEGIN_NVC0(push, NVC0_3D(CB_BIND(4)), 1);
PUSH_DATA (push, 0x11);
- BEGIN_NVC0(push, SUBC_3D(0x2608), 1);
+ BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
PUSH_DATA (push, 1);
}
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 4c3bb0f..607e97b 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -12,6 +12,7 @@
/* subchannel assignments, compatible with kepler's fixed lay...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...AccelInit3D_NVC0(ScrnInfoPtr pScrn)
> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
> PUSH_DATA (push, 1);
> + } else {
> + /* Use new TIC format. Not strictly necessary for GM20x+ */
> + IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
> + if (pNv->dev->chipset >= 0x120) {
> + /* Use center sample locations. */
> + BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
> + PUSH_DATA (push, 0x88888888);
> + PUSH_DATA (push, 0x88888888);
> + PUSH_DATA (push, 0x88888888);
> + PUSH_DATA (push, 0...
2014 Dec 31
0
[PATCH] nv50,nvc0: set vertex id base to index_bias
...@@ -608,6 +608,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
PUSH_DATA (push, 1);
+ BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
+ PUSH_DATA (push, 0);
+ if (screen->base.class_3d >= NV84_3D_CLASS) {
+ BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+ PUSH_DATA (push, 0);
+ }
+
PUSH_KICK (push);
}
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 5a4a457..c1590ee 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/driver...
2014 Jul 10
3
[PATCH 0/3] nvc0: ARB_(multi_)draw_indirect support
The main patches are from Christoph. Unfortunately they're a little beyond my
understanding of all the vertex-related details, but they generally seemed
fine. I'm just going to push these unless someone steps up to review them.
Christoph Bumiller (2):
nvc0: add support for indirect drawing
nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYS
Ilia Mirkin (1):
nouveau: check if
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...>offset + MISC_OFFSET) >> 32);
> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
> PUSH_DATA (push, 1);
> + } else {
> + /* Use new TIC format. Not strictly necessary for GM20x+ */
Yes, but it's also enabled by default in mesa, looks fine.
> + IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
> + if (pNv->dev->chipset >= 0x120) {
> + /* Use center sample locations. */
> + BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
> + PUSH_DATA (push, 0x88888888);
> + PUSH_DATA (push, 0x88888888);
> + PUSH_DATA (push, 0x88888888);
> + PUSH_DATA (push, 0...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...ET) >> 32);
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>> PUSH_DATA (push, 1);
>> + } else {
>> + /* Use new TIC format. Not strictly necessary for GM20x+
>> */
>> + IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
>> + if (pNv->dev->chipset >= 0x120) {
>> + /* Use center sample locations. */
>> + BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
>> + PUSH_DATA (push, 0x88888888);
>> +...
2014 Feb 13
2
[PATCH] nouveau: fix chipset checks for nv1a by using the oclass instead
..._3D(UNK01AC), 2);
PUSH_DATA (push, fifo->vram);
PUSH_DATA (push, fifo->vram);
@@ -257,7 +257,7 @@ nv10_hwctx_init(struct gl_context *ctx)
PUSH_DATA (push, 1);
}
- if (context_chipset(ctx) >= 0x11) {
+ if (context_eng3d(ctx)->oclass >= NV15_3D_CLASS) {
BEGIN_NV04(push, SUBC_3D(0x120), 3);
PUSH_DATA (push, 0);
PUSH_DATA (push, 1);
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
index 19769e5..fb66b2d 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
@@...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...ccel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ }
}
BEGIN_NVC0...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...ccel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ }
}
BEGIN_NVC0...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...));
>> PUSH_DATA (push, 1);
>> + } else {
>> + /* Use new TIC format. Not strictly necessary for GM20x+
>> */
>
>
> Yes, but it's also enabled by default in mesa, looks fine.
>
>
>> + IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
>> + if (pNv->dev->chipset >= 0x120) {
>> + /* Use center sample locations. */
>> + BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
>> + PUSH_DATA (push, 0x88888888);
>> +...
2012 May 12
7
[Patches] mesa/nv30: Diverse set of patches that improve NV3x render quality V2
A reworked version of 3 out of 4 patches mentioned earlier.
[1/4]: Fixes nearly all piglit vertprog testcases, due to now being able to pass the results on to the fragment shader. V2: rename samplers to texcoords.
[2/4]: Fixes shader compiler assertion errors, as some source registers do not exist for certain operations. Fixes several piglit tests when mesa is compiled with --enable-debug
[3/4]:
2014 Jan 27
0
[PATCH] nv30: don't overwrite blend color setting for r32/r16 float formats
...ium/drivers/nouveau/nv30/nv30_state_validate.c
index f227559..b5584c8 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c
@@ -190,7 +190,7 @@ nv30_validate_blend_colour(struct nv30_context *nv30)
BEGIN_NV04(push, SUBC_3D(0x037c), 1);
PUSH_DATA (push, (util_float_to_half(rgba[2]) << 0) |
(util_float_to_half(rgba[3]) << 16));
- break;
+ return;
default:
break;
}
--
1.8.3.2
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2014 Oct 21
0
[PATCH v2] nv50: Handle ARB_conditional_render_inverted and enable it
...GIN_NV04(push, NV50_3D(COND_MODE), 1);
- PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
+ PUSH_DATA (push, cond);
return;
}
- q = nv50_query(pq);
- if (mode == PIPE_RENDER_COND_WAIT ||
- mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
+ if (wait) {
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
PUSH_DATA (push, 0);
}
+ PUSH_SPACE(push, 8);
+ PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3);
PUSH_DATAh(push, q->bo->offset + q->offset);
PUSH_DATA (push, q->bo->o...
2016 Feb 15
2
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...ng3d->oclass >= GM107_3D_CLASS) {
> + screen->tic.maxwell = true;
> + if (screen->eng3d->oclass == GM107_3D_CLASS) {
> + screen->tic.maxwell =
> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
> + IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
> + }
> + }
>
> BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
> PUSH_DATAh(push, screen->txc->offset + 65536);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
&g...
2015 Dec 14
6
[Bug 93373] New: sometimes hickup with persistent garbaby
https://bugs.freedesktop.org/show_bug.cgi?id=93373
Bug ID: 93373
Summary: sometimes hickup with persistent garbaby
Product: xorg
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: minor
Priority: medium
Component: Driver/nouveau
Assignee:
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...1);
+ if (screen->eng3d->oclass >= GM107_3D_CLASS) {
+ screen->tic.maxwell = true;
+ if (screen->eng3d->oclass == GM107_3D_CLASS) {
+ screen->tic.maxwell =
+ debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
+ IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
+ }
+ }
BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset + 65536);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 40c9c7a..f34fabd 100644...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...= GM107_3D_CLASS) {
>> + screen->tic.maxwell = true;
>> + if (screen->eng3d->oclass == GM107_3D_CLASS) {
>> + screen->tic.maxwell =
>> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
>> + IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
>> + }
>> + }
>>
>> BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
>> PUSH_DATAh(push, screen->txc->offset + 65536);
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouve...
2016 Jun 05
0
[RFC PATCH] nouveau: add locking
...nouveau_context_update_frame_stats(nouveau_context(pipe));
}
@@ -47,10 +49,12 @@ nv50_texture_barrier(struct pipe_context *pipe)
{
struct nouveau_pushbuf *push = nv50_context(pipe)->base.pushbuf;
+ pipe_mutex_lock(nouveau_context(pipe)->screen->push_mutex);
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
PUSH_DATA (push, 0x20);
+ pipe_mutex_unlock(nouveau_context(pipe)->screen->push_mutex);
}
static void
@@ -107,6 +111,7 @@ nv50_emit_string_marker(struct pipe_context *pipe, const cha...