Displaying 18 results from an estimated 18 matches for "sub7".
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2013 Apr 26
0
[LLVMdev] 'LowerDbgDeclare' in Instruction combining affects scope information
...ta !24), !dbg !38
call void @llvm.dbg.value(metadata !{i32* %r}, i64 0, metadata !24), !dbg !38
call void @llvm.dbg.value(metadata !{i32* %r}, i64 0, metadata !24), !dbg !38
call void @llvm.dbg.value(metadata !{i32* %r}, i64 0, metadata !24), !dbg !38
%2 = load i32* %r, align 4, !dbg !38
%sub7 = sub i32 0, %2, !dbg !38
call void @llvm.dbg.value(metadata !{i32 %sub7}, i64 0, metadata !24), !dbg !38
call void @llvm.dbg.value(metadata !{i32 %sub7}, i64 0, metadata !24), !dbg !38
call void @llvm.dbg.value(metadata !{i32 %sub7}, i64 0, metadata !24), !dbg !38
call void @llvm.dbg.value...
2016 Aug 23
2
How to describe the RegisterInfo?
...(add (decimate (shl gpr_b, 2), 4)),
(add (decimate (shl gpr_b, 3), 4))]>;
// simd byte use stride 2 register as stride 1 does not support useful ALU
instruction
def gpr_b_simd8 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6,
sub7],
[(add (decimate gpr_b, 16)),
(add (decimate (shl gpr_b, 2), 16)),
(add (decimate (shl gpr_b, 4), 16)),
(add (decimate (shl gpr_b, 6), 16)),...
2003 Nov 05
0
Re: [S] LME - fixed effects model and missing values
...ok like this:
> MAT<- structure(c(23, 24, 6, 19, 16, 20, 13, 11, NA, 8, NA, 21, 19, 15,
11, NA, 10, 12, 16, 30, 13, 16, NA, NA, NA, NA, 28, 6), .Dim = c(7, 4),
.Dimnames = list(c("SUB1", "SUB2", "SUB3", "SUB4", "SUB5", "SUB6",
"SUB7"), c("BDI0", "BDI3", "BDI6", "BDI12")))
> MAT
BDI0 BDI3 BDI6 BDI12
SUB1 23 11 11 16
SUB2 24 NA NA NA
SUB3 6 8 10 NA
SUB4 19 NA 12 NA
SUB5 16 21 16 NA
SUB6 20 19 30 28
SUB7 13 15 13...
2019 Sep 30
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...; if.end4: ; preds = %if.then2, %entry
> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
> %mul = mul nsw i32 %b.addr.0, %spec.select
> %tobool5 = icmp eq i16 %neg.1, 0
> %sub7 = sub nsw i32 0, %mul
> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
> ret i32 %spec.select18
> }
>
> attributes #0 = { norecurse nounwind optsize readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false&q...
2009 Apr 09
2
better way of recoding factors in data frame?
...the merged dataframe:
> myFrame2
???SubjCode SubjSex? ? ? ? ? Sex
1? ? ? sub1? ? ???M? ? ? ???<NA>
2? ? ? sub2? ? ???F? ? ? ???<NA>
3? ? ? sub3? ? ???M? ? ? ???Male
4? ? ? sub4? ? ???M? ? ? ???<NA>
5? ? ? sub5? ? ???F? ? ? ???<NA>
6? ? ? sub6? ? ???F? ? ???Female
7? ? ? sub7? ? ? ? ? ? ? ???<NA>
8? ? ? sub8? ? ? ? ? ? ? ???<NA>
9? ? ? sub9? ? ? ???Not Recorded
10? ? sub10? ? ? ???Not Recorded
I then apply the following:
> myFrame2$SubjSex <- factor(myFrame2$SubjSex, levels = c('M','F'))
> myFrame2$SubjSex <- factor(myFrame2$Sub...
2019 Sep 29
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...> if.end4: ; preds = %if.then2, %entry
> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
> %mul = mul nsw i32 %b.addr.0, %a.addr.0
> %tobool5 = icmp eq i16 %neg.1, 0
> %sub7 = sub nsw i32 0, %mul
> %res.0 = select i1 %tobool5, i32 %mul, i32 %sub7
> ret i32 %res.0
> }
>
> The offending part here is this: %a.lobit = lshr i32 %a, 31 . Instead of just creating a “select” instruction, as the original code suggested with the if (a < 0) { neg = 1;} stat...
2012 Jul 11
2
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
...;=f,f,f,f"(float
%sub, float 4.097000e+03, float %0) nounwind
%2 = tail call float asm "mad.f32 $0, $1, $2, $3;", "=f,f,f,f"(float %0,
float 4.097000e+03, float %1) nounwind
%y5 = getelementptr inbounds %struct.float2* %y, i64 0, i32 1
%3 = load float* %y5, align 4
%sub7 = fsub float -0.000000e+00, %3
%4 = tail call float asm "mad.f32 $0, $1, $2, $3;", "=f,f,f,f"(float
%sub7, float 4.097000e+03, float %3) nounwind
%5 = tail call float asm "mad.f32 $0, $1, $2, $3;", "=f,f,f,f"(float %3,
float 4.097000e+03, float %4) nounwi...
2019 Sep 30
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...;
> if.end4: ; preds = %if.then2,
> %entry
> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
> %mul = mul nsw i32 %b.addr.0, %spec.select
> %tobool5 = icmp eq i16 %neg.1, 0
> %sub7 = sub nsw i32 0, %mul
> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
> ret i32 %spec.select18
> }
>
> attributes #0 = { norecurse nounwind optsize readnone
> "correctly-rounded-divide-sqrt-fp-math"="false"
> "disable-tail-calls"="f...
2009 Nov 27
2
using reshape to do ANOVA mixed models
Hi,
I just started with R and I found that there are many options to rearrange
the data to do mixed models.
I want to use the reshape function. I have 2 between subject variables and
one within.
I was able to change the data structure but still - the result of the aov
functions are calculating everything as a within subject.
the table looks like this:
SerialNo breed treatment distance_1
2019 Oct 01
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...; preds = %if.then2, %entry
>>> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
>>> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
>>> %mul = mul nsw i32 %b.addr.0, %spec.select
>>> %tobool5 = icmp eq i16 %neg.1, 0
>>> %sub7 = sub nsw i32 0, %mul
>>> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
>>> ret i32 %spec.select18
>>> }
>>>
>>> attributes #0 = { norecurse nounwind optsize readnone "correctly-rounded-divide-sqrt-fp-math"="false" "d...
2012 Nov 09
0
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
...t; float 4.097000e+03, float %0) nounwind
> %2 = tail call float asm "mad.f32 $0, $1, $2, $3;", "=f,f,f,f"(float %0,
> float 4.097000e+03, float %1) nounwind
> %y5 = getelementptr inbounds %struct.float2* %y, i64 0, i32 1
> %3 = load float* %y5, align 4
> %sub7 = fsub float -0.000000e+00, %3
> %4 = tail call float asm "mad.f32 $0, $1, $2, $3;", "=f,f,f,f"(float
> %sub7, float 4.097000e+03, float %3) nounwind
> %5 = tail call float asm "mad.f32 $0, $1, $2, $3;", "=f,f,f,f"(float %3,
> float 4.097000e+...
2019 Sep 25
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
Changing the order of the checks in CodeGenPrepare::optimizeSelectInst()
sounds good to me.
But you may need to go further for optimum performance. For example, we may
be canonicalizing math/logic IR patterns into 'select' such as in the
recent:
https://reviews.llvm.org/D67799
So if you want those to become ALU ops again rather than branches, then you
need to do the transform later in
2006 Nov 01
1
How to rsync only specified subdirectories in the source folder?
...ectories named sub1~sub10(each including
subdirectories and files too),and file1~file10,how can I rsync only sub2 and
sub 3 to the target?
/---- MyFolder
|---------- sub1
|---------- sub2
|---------- sub3
|---------- sub4
|---------- sub5
|---------- sub6
|---------- sub7
|---------- sub8
|---------- sub9
|---------- sub10
|---------- file1
|---------- file2
|---------- file3
|---------- file4
|---------- file5
|----------------------
rsync -av --delete --include "/sub2/" --include "/sub3/" /MyFolder/ /dest/
th...
2016 Aug 23
2
How to describe the RegisterInfo?
Hi Escha,
Great to have your comment! Do you have any specific reason for not doing
like this?
I am not sure whether I understand your point correctly. For "just model
one thread",
do you mean "only considering ONE of the 8/16 working lanes that running in
lock-step way"??
For my case, may be something like I only need to define r0~r127 as
register for i32 register (each r#
2019 Oct 03
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...; preds = %if.then2, %entry
>>>> %b.addr.0 = phi i32 [ %sub3, %if.then2 ], [ %b, %entry ]
>>>> %neg.1 = phi i16 [ %1, %if.then2 ], [ %0, %entry ]
>>>> %mul = mul nsw i32 %b.addr.0, %spec.select
>>>> %tobool5 = icmp eq i16 %neg.1, 0
>>>> %sub7 = sub nsw i32 0, %mul
>>>> %spec.select18 = select i1 %tobool5, i32 %mul, i32 %sub7
>>>> ret i32 %spec.select18
>>>> }
>>>>
>>>> attributes #0 = { norecurse nounwind optsize readnone "correctly-rounded-divide-sqrt-fp-math"="...
2012 Nov 11
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
Hi Susan,
It looks like the bitcode you have attached is corrupted. You should make
sure to attach it as a binary file. Alternatively you can attach the LLVM
assembly as text. You can generate an assembly file from bitcode with:
llvm-dis -o <asm file> <bitcode>
Regards,
Lang.
On Fri, Nov 9, 2012 at 11:15 AM, Susan Horwitz <horwitz at cs.wisc.edu> wrote:
> Thanks Lang,
2012 Nov 11
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
....)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %x.0)
%add = add nsw i32 %x.0, 5
%mul = mul nsw i32 %x.0, 2
%sub = sub nsw i32 %mul, 1
%mul3 = mul nsw i32 %add, %sub
%add4 = add nsw i32 %x.0, %mul3
%div5 = sdiv i32 %add4, %x.0
%add6 = add nsw i32 5, %add
%sub7 = sub nsw i32 %div5, %add6
%add8 = add nsw i32 %add4, %sub7
%add9 = add nsw i32 %add8, %x.0
%add10 = add nsw i32 %add9, %add
%add11 = add nsw i32 %add10, %sub
%call12 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([37 x i8]* @.str1, i32 0, i32 0), i32 %add4, i32 %sub7, i32 %ad...
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...c.ptr.10.i, align 2, !tbaa !5
store i16 0, i16* %incdec.ptr.11.i, align 2, !tbaa !5
br label %if.end74
if.else: ; preds = %if.then60
%8 = load i16* %incdec.ptr.i, align 2, !tbaa !5
%conv70 = zext i16 %8 to i32
%sub.neg = sub i32 -65535, %call62
%sub71 = add i32 %sub.neg, %conv70
%conv72 = trunc i32 %sub71 to i16
store i16 %conv72, i16* %incdec.ptr.i, align 2, !tbaa !5
br label %if.end74
if.end74: ; preds = %if.then65, %if.else, %if.end48
call fastcc void @emovo(i16* %arraydecay, i16* %y)
br lab...