search for: strexd

...Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Thus I believe the safest solution is to always force 64-bit operands into even/odd pairs for any inline asm. In other words, we should probably do som...

On 7/16/14, 6:09 PM, sgundapa wrote: > I see a couple of issues here. > > If I include .S files for ARM, the –no-integrated-as path complains about > Assembler errors. > > The integrated-as path works fine though. > These are very likely just differences between the old ARM assembler syntax and the new 'Unified' syntax. Can you use an assembler that accepts UAL

...<<<<<<<<<<<<<<<< 19c: e023700e eor r7, r3, lr 1a0: e0022003 and r2, r2, r3 1a4: e0087007 and r7, r8, r7 1a8: e1820007 orr r0, r2, r7 1ac: e1b42e9f ldaexd r2, r3, [r4] 1b0: e1a46f90 strexd r6, r0, [r4] 1b4: e3560000 cmp r6, #0 1b8: 1afffffb bne 1ac <xxxxx+0x1ac> 1bc: 1a000002 bne 1cc <xxxx+0x1cc> <<<<<<<<<<<<<<<<<<< 1c0: e1a00005 mov r0, r5 1c4: e3a01001...

On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: > One possible fix, which I have tested, is to look for the specific > instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in > addition to the 'H' modifier. However, there are probably other > creative ways in which inline asm might rely on the specific pairing. > Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to have something b...

Hi, I'm wondering if LLVM plans to support paired register constraints for 64-bit data. Take ARM for example, the atomic i64 value read/write instuctions: ldrexd/strexd, require aligned register pairs (even/odd). Currently, in LLVM ARM (ARMISelDAGToDAG.cpp), ldrexd/strexd get hard coded registers (R0,R1) before register allocation via intrinsic. It would be neater if there is a register constraint and register class that support 64-bit data and let the re...

...weimingz at codeaurora.org Subject: Re: Problems with 64-bit register operands of inline asm on ARM On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to have something better tha...

...Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Thus I believe the safest solution is to always force 64-bit operands into even/odd pairs for any inline asm. In other words, we should probably do som...

....org > Subject: Re: Problems with 64-bit register operands of inline asm on ARM > > On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: > One possible fix, which I have tested, is to look for the specific > instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in > addition to the 'H' modifier. However, there are probably other > creative ways in which inline asm might rely on the specific pairing. > > Hi Mans, > > Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to...

LLVM can model some quite complicated register banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also assign assembly names to such pseudo-registers, again from ARM: SPR: (s...

...no compile-time regressions. Chad On May 22, 2013, at 2:20 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > LLVM can model some quite complicated register banks now, and we even use registers to model some encoding constraints. > > For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. > > Sometimes ISAs also assign assembly names to such pseudo-registers, again from ARM...