search for: strex

All, I've attached a small patch that adds a new early-clobber operand constraint option to TableGen and would like to get feedback before proceding. As background, the ARM store-exclusive instruction (STREX) stores a success result code in a register operand, and that register cannot be the same register as either the source of the value to be stored, or the base address. Specifically. STREX Rd, Rm, [Rn] // Store Rm to the address contained in Rn, store zero in Rd if successful, one in Rd...

On Tuesday 15 December 2009 18:01, Jim Grosbach wrote: > For a usage example, I've included in the patch the modification to > use the constraint for the STREX ARM instruction. Your example is: constraints = "@early $success" Why not spell it as: constraints = "$success != $src", "$success != $ptr" The grammar would change to something like: constraint: operand '!=' operand | operand '=' operand This...

...lder) const { >> if (Subtarget->hasV7Ops()) { >> Module *M = Builder.GetInsertBlock()->getParent()->getParent(); >> Builder.CreateCall(llvm::Intrinsic::getDeclaration(M, >> Intrinsic::arm_clrex)); >> } >> } For v6, I guess we could do a fake strex to some dummy global? Anyway, r248640, sorry about that! -Ahmed >> -Rich >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > >

...> { > unsigned long tmp; > int result; > > - __asm__ __volatile__("@ atomic_add\n" > + __asm__ __volatile__("@ atomic_inc\n" > "1: ldrex %0, [%3]\n" > " add %0, %0, #1\n" > " strex %1, %0, [%3]\n" > @@ -130,7 +121,7 @@ static inline void atomic_dec(uint32_t *v) > unsigned long tmp; > int result; > > - __asm__ __volatile__("@ atomic_sub\n" > + __asm__ __volatile__("@ atomic_dec\n" > "1: ldr...

Hello community, I faced with bug in multithread environment in objective C code which using dispatch_async and block, __sync_add_and_fetch increments global variable. But in case of many..many threads> 5, after every __sync_add_and_fetch got damaged ... int32_t count = 0; ... int main(int argc, char *argv[]) {    for (i = 1; i < 32; ++i) {      ...         char* name;        

...bjc block for global variable on ARM > From: t.p.northover at gmail.com > To: alexey.perevalov at hotmail.com > CC: llvmdev at cs.uiuc.edu > >> in disas I see dmb ish instruction, but I don't know is it enough. > > There should be 2 dmb instructions: one before the ldrex/strex loop > and one after. But I wouldn't expect dropping one to actually cause a > problem in the code you posted. Yes, there are two dmb's => 0x00008ed8 <+224>:    dmb    ish    0x00008edc <+228>:    movw    r1, #10800    ; 0x2a30    0x00008ee0 <+232>:    movt    r1,...

On 10 May 2014, at 13:53, Tim Northover <t.p.northover at gmail.com> wrote: > It doesn't make sense for everything though, particularly if you want > target-specific IR to simply not exist. What would you map ARM's > "ldrex" to on x86? This isn't a great example. Having load-linked / store-conditional in the IR would make a number of transforms related to

...nbits.xensource.com/gitweb?p=osstest.git;a=summary Not pushing. ------------------------------------------------------------ commit 08d89ac8bd7f43d897cdffe85b236c71d3408e16 Author: Ian Campbell <ian.campbell@citrix.com> Date: Fri Jul 19 16:20:10 2013 +0100 xen: arm: retry trylock if strex fails on free lock. This comes from the Linux patches 15e7e5c1ebf5 for arm32 and 4ecf7ccb1973 for arm64 by Will Deacon and Catalin Marinas respectively. The Linux commit message says: An exclusive store instruction may fail for reasons other than lock contentio...

tags 618616 pending stop On Wed, 16 Mar 2011, Lo?c Minier wrote: > I've fixed this in Ubuntu with the attached patch, but didn't find > where to upstream it; since you're a klibc upstream developer and since > it probably already affects Debian, I figured it was probably best to > send it here :-) thank you applied after review by hpa and pushed out to klibc git.

Hi, I was compiling libc++ with a recent TOT (248571) and when I got to the ARMv6, I got a code generation error in memory.cpp: fatal error: error in backend: Cannot select: intrinsic %llvm.arm.clrex ecc: error: clang frontend command failed with exit code 70 (use -v to see invocation) clang version 3.8.0 (trunk) It looks as if the newly added emitAtomicCmpXchgNoStoreLLBalance() function is

...9001 str r0, [sp, #4]0000003e 6808 ldr r0, [r1, #0]00000040 f1020108 add.w r1, r2, #8 @ 0x800000044 f8cc1000 str.w r1, [ip]00000048 f3bf8f5a dmb ishst0000004c 9901 ldr r1, [sp, #4]0000004e e8512f00 ldrex r2, [r1]00000052 9200 str r2, [sp, #0]00000054 441a add r2, r300000056 e8412c00 strex ip, r2, [r1]0000005a f1bc0f00 cmp.w ip, #0 @ 0x00000005e d1f6 bne.n 0x4e... What happens in the code between 4e and 5e is an atomic check of a variable by the inlined __exchange_and_add. The problem is that the result read by ldrex is stored by the inline optimization on the stack for further u...

On 10 May 2014, at 18:14, Tim Northover <t.p.northover at gmail.com> wrote: >> The easiest solution would be to extend the cmpxchg instruction with a >> weak variant. It is then trivial to map load, modify, weak-cmpxchg to >> load-linked, modify, store-conditional (that is what weak cmpxchg was >> intended for in the C[++]11 memory model). > > That would

...wrote: > Actually, I really agree there. I considered it recently, but decided > to leave it as an intrinsic for now (the new IR expansion pass happens > after most optimisations so there wouldn't be much benefit, but if we > did it earlier and the mid-end understood what an ldrex/strex meant, I > could see code getting much better). > > Load linked would be fairly easy (perhaps even written as "load > linked", a minor extension to "load atomic"). Store conditional would > be a bigger change since stores don't return anything at the moment;...

I tried to build VMKit on an ARM device today (a Sheevaplug - armv5te) (native, not cross compiled), and got this error: llvm[3]: Building LLVM assembly with /home/debio/build/vmkit-build/vmkit/lib/Mvm/Runtime/LLVMAssembly.ll /home/debio/build/vmkit-build/vmkit/lib/Mvm/Runtime/LLVMAssembly64.ll ExpandIntegerResult #0: 0x16fbf88: i64,ch = AtomicCmpSwap 0x16e8d84, 0x16fbf00, 0x16fc3c8,

On Dec 15, 2009, at 5:08 PM, David Greene wrote: > On Tuesday 15 December 2009 18:01, Jim Grosbach wrote: > >> For a usage example, I've included in the patch the modification to >> use the constraint for the STREX ARM instruction. > > Your example is: > > constraints = "@early $success" > > Why not spell it as: > > constraints = "$success != $src", "$success != $ptr" > This was my first thought as well; however, I decided against it. I think it'...

...> /llvm-toolchain-3.8-3.8/projects/compiler-rt/lib/builtins/arm/sync_fetch_and_add_4.S:20: > Error: cannot honor width suffix -- `add r2,r0,r1' > /llvm-toolchain-3.8-3.8/projects/compiler-rt/lib/builtins/arm/sync_fetch_and_add_4.S:20: > Error: selected processor does not support `strex r3,r2,[r12]' in > Thumb mode > /llvm-toolchain-3.8-3.8/projects/compiler-rt/lib/builtins/arm/sync_fetch_and_add_4.S:20: > Error: selected processor does not support `dmb' in Thumb mode > projects/compiler-rt/lib/builtins/CMakeFiles/clang_rt.builtins-armhf.dir/build.make:1097:...

The following patches shave some rough edges off the tools build system to allow cross compiling for at least arm32 and arm64 based on the Debian/Ubuntu multiarch infrastructure. They also add the necessary fixes to build for arm64 (which I have only tried cross, not native). I have posted some instructions on how to compile with these patches on the wiki:

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

...svr1.cpp src/olesvr2.cpp src/oletsvr.cpp src/oletyplb.cpp src/oleui1.cpp src/oleui2.cpp src/oleunk.cpp src/olevar.cpp src/olevar1.cpp src/oleverb.cpp src/plex.cpp src/ppgcolor.cpp src/ppgfont.cpp src/ppgpict.cpp src/ppgstock.cpp src/sockcore.cpp src/strcore.cpp src/strex.cpp src/thrdcore.cpp src/timecore.cpp src/tooltip.cpp src/trckrect.cpp src/validadd.cpp src/viewcmn.cpp src/viewcore.cpp src/viewedit.cpp src/viewform.cpp src/viewhtml.cpp src/viewoled.cpp src/viewprev.cpp src/viewprnt.cpp src/viewrich.cpp src/viewscrl.cpp src/winbtn...