search for: srctype

Displaying 16 results from an estimated 16 matches for "srctype".

Did you mean: srcatype
2009 Jun 13
0
[LLVMdev] Regular Expressions
...ss", "f32", "i32">; > > [Meanwhile, down in the guts...] > > class fp_cvt_scalar_VXSnrr< > // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr > bits<8> opc, > string OpcodeStr, > SDNode OpNode, > string DstType, > string SrcType, > int CustomPatterns = 0, > list<dag> patterns = [], > string asm = "" >> : fp_unary_vxs_n_rm_rr< > opc, > !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",! > patsubst("^i([0-9]+)","GR$1",DstType)...
2009 Jun 11
2
[LLVMdev] Regular Expressions
...;cvtsi2ss", sint_to_fp, "cvtsi2ss", "f32", "i32">; [Meanwhile, down in the guts...] class fp_cvt_scalar_VXSnrr< // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr bits<8> opc, string OpcodeStr, SDNode OpNode, string DstType, string SrcType, int CustomPatterns = 0, list<dag> patterns = [], string asm = "" >: fp_unary_vxs_n_rm_rr< opc, !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",!patsubst("^i([0-9]+)","GR$1",DstType))), [...] Basically, the code k...
2009 Dec 03
2
[LLVMdev] Duplicate Label in Generates ISel
...licate case value llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here This seems to happen because of a pattern I added for VEXTRACTF128 which uses extract_subreg: [(set DSTREGCLASS:$dst, (DSTTYPE (extract_subreg (vector_shuffle (SRCTYPE undef), (SRCTYPE SRCREGCLASS:$src1), VEXTRACTF128_shuffle_mask:$src2), x86_subreg_128bit)))], def x86_subreg_128bit : PatLeaf<(i32 1)>; Curiously, I have analogous patterns for VINSERTF128 that use insert_subreg but it doesn'...
2009 Jun 15
2
[LLVMdev] Regular Expressions
...e fp_cvt_scalar_VXSnrr to be something like this: > >> class fp_cvt_scalar_VXSnrr< >> // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr >> bits<8> opc, >> string OpcodeStr, >> SDNode OpNode, >> X86ValueType DstType, >> X86ValueType SrcType, >> int CustomPatterns = 0, >> list<dag> patterns = [], >> string asm = "" >>> : fp_unary_vxs_n_rm_rr< >> opc, DstType.RegClass, > > This lets you encode whatever you want as properties of the dependent > class, makes everything...
2015 Feb 23
2
[LLVMdev] Eliminating redundant loads
...lue** %k, align 8 %6 = load %ravi.TValue** %base, align 8 %srcvalue = getelementptr inbounds %ravi.TValue* %5, i64 0, i32 0, i32 0 %destvalue = getelementptr inbounds %ravi.TValue* %6, i64 0, i32 0, i32 0 %7 = load double* %srcvalue, align 8 store double %7, double* %destvalue, align 8 %srctype = getelementptr inbounds %ravi.TValue* %5, i64 0, i32 1 %desttype = getelementptr inbounds %ravi.TValue* %6, i64 0, i32 1 %8 = load i32* %srctype, align 4 store i32 %8, i32* %desttype, align 4 %9 = load %ravi.TValue** %base, align 8 %srcvalue1 = getelementptr inbounds %ravi.TValue* %5, i6...
2009 Dec 03
0
[LLVMdev] Duplicate Label in Generates ISel
...6/X86GenDAGISel.inc:91442: error: previously used here > > This seems to happen because of a pattern I added for VEXTRACTF128 which > uses extract_subreg: > > [(set DSTREGCLASS:$dst, > (DSTTYPE (extract_subreg > (vector_shuffle > (SRCTYPE undef), > (SRCTYPE SRCREGCLASS:$src1), > VEXTRACTF128_shuffle_mask:$src2), > x86_subreg_128bit)))], > > def x86_subreg_128bit : PatLeaf<(i32 1)>; Whoops, I forgot to fill in types: (outs VR128:$dst), (ins VR129:$src...
2015 Feb 23
2
[LLVMdev] Eliminating redundant loads
...0 = type { %ravi.TValue*, i32*, i64 } .... %6 = load %ravi.TValue** %base %srcvalue = getelementptr inbounds %ravi.TValue* %5, i32 0, i32 0, i32 0 %destvalue = getelementptr inbounds %ravi.TValue* %6, i32 0, i32 0, i32 0 %7 = load double* %srcvalue store double %7, double* %destvalue %srctype = getelementptr inbounds %ravi.TValue* %5, i32 0, i32 1 %desttype = getelementptr inbounds %ravi.TValue* %6, i32 0, i32 1 %8 = load i32* %srctype store i32 %8, i32* %desttype %9 = load %ravi.TValue** %base %10 = getelementptr inbounds %ravi.TValue* %9, i32 1 %11 = getelementptr inbounds...
2010 Sep 23
1
strange behaviour of callNextMethod in S4 methods
...able,"time","NC_CHAR",object at time) } ) Define an inherited method for class OPSource: setMethod("ncputVar",signature(nc="NetCDF",variable="ANY",object="OPSource"), def=function(nc,variable,object) { att.put.nc(nc,variable,"srctype","NC_CHAR","OPSource") att.put.nc(nc,variable,"oporig","NC_CHAR",object at oporig) callNextMethod() } ) A call to ncputVar with an OPSource object causes an error saying object is not present. But if the method definition is changed like this:...
2015 Feb 22
2
[LLVMdev] Eliminating redundant loads
On 22 February 2015 at 20:58, David Jones <djones at xtreme-eda.com> wrote: > Not sure if this is your problem, but it was mine: > > You must create (or obtain) a DataLayout *and install it into the Module*. > > It is possible to generate machine code for IR and not install the > DataLayout into the Module. Rather, the DataLayout is used locally at the > point where code
2009 Jun 15
0
[LLVMdev] Regular Expressions
On Jun 15, 2009, at 11:33 AM, David Greene wrote: > To reduce redundancy, developers must be able to write generic > patterns > like this: > > [(set DSTREGCLASS:$dst, // rr, rrr > (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))), > (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))], > > The substitution then fills in the appropriate types, etc. based > on which variant (32-bit, 64-bit, AVX, etc.) is being produced. > > I suppose you could argue that ad...
2015 Feb 23
3
[LLVMdev] Eliminating redundant loads
On 23 February 2015 at 01:29, Kamal Sharma <kgs1.rice at gmail.com> wrote: > Hi Dibyendu, > > It would be very helpful if you could post the original source code or > snippet. > That way, one can investigate deeper to understand the problem. > > Regards, > Kamal Sharma > Hi Kamal, Sure. I guess I ought to create a test that one can look in isolation. I am
2010 Sep 07
0
[LLVMdev] Intrinsic prototype has incorrect number of arguments!
On Sep 7, 2010, at 8:03 AM, F van der Meeren wrote: > Hello, > > I have a question, what is wrong with the following code? > > declare void @llvm.memcpy.p0i64.p0i64.i8(i64*, i64*, i8, i32, i1) nounwind > > ... > > call void @llvm.memcpy.p0i64.p0i64.i8(i64* %19, i64* %21, i8 %17, i32 0, i1 false) > > ... > > > According to the compiler this is the
2010 Sep 07
2
[LLVMdev] Intrinsic prototype has incorrect number of arguments!
...set(methodName, 0, methodNameSize); sprintf(methodName, methodNameTemplate, dstSize, srcSize, lengthSize); // Search for the function or create it. if((function = LLVMGetNamedFunction(module, methodName)) == NULL) { LLVMTypeRef paramTypes [] = { dstType, srcType, lengthType, LLVMInt32TypeInContext(context), LLVMInt1TypeInContext(context), }; functionType = LLVMFunctionType(LLVMVoidTypeInContext(context), paramTypes, numberOfArguments, false); function = LLVMAddFunction(module...
2009 Jun 11
0
[LLVMdev] Regular Expressions
On Jun 9, 2009, at 12:39 PM, David Greene wrote: > On Tuesday 09 June 2009 14:34, Dan Gohman wrote: >> Can you describe what problem you're trying to solve here? Does it >> really need Regular Expressions? > > Yes. I want TableGen to be able to infer lots of stuff > programmatically. > This helps tremendously when specifying things like, oh, AVX. :) I
2009 Jun 09
3
[LLVMdev] Regular Expressions
On Tuesday 09 June 2009 14:34, Dan Gohman wrote: > Can you describe what problem you're trying to solve here? Does it > really need Regular Expressions? Yes. I want TableGen to be able to infer lots of stuff programmatically. This helps tremendously when specifying things like, oh, AVX. :) We could invent our own pattern matching syntax, but why?
2010 Sep 07
4
[LLVMdev] Intrinsic prototype has incorrect number of arguments!
Hello, I have a question, what is wrong with the following code? declare void @llvm.memcpy.p0i64.p0i64.i8(i64*, i64*, i8, i32, i1) nounwind ... call void @llvm.memcpy.p0i64.p0i64.i8(i64* %19, i64* %21, i8 %17, i32 0, i1 false) ... According to the compiler this is the error, but I seem to miss where exactly my fault is. Intrinsic prototype has incorrect number of arguments! void (i64*,