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It appears that it's impossible to duplicate a node in the dag. For example, there is some code: b = a * a; // a is a global int A LD node is generated for A and it goes into both Operand 0 and 1 of the MUL node. The issue is I'm trying to match a pattern of: set dstReg:$dstD (OpNode (srcAType (load addr32:$srcA)), (srcBType (load addr32:$srcB))) so basically a mem, mem, reg operation. The issue is this pattern won't match in the above example because there is only one LD generated for 'a'. I tried to duplicate the LD in the dag but it doesn't show up, it always reduces...

...quot;, unsignedSub, LOADRegs, >> GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; >> >> multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, >> RegisterClass srcAReg, RegisterClass srcBReg, >> RegisterClass dstReg, ValueType srcAType, ValueType >> srcBType, ValueType dstType, >> Operand ImmOd, ImmLeaf imm_type> >> { >> .... >> def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx, >> [(directStore (dstType (OpNode >> i...

Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, [(set...

> On Jun 15, 2015, at 7:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > To be more specific: > > We have some operators that we are currently implementing as intrinsics, for example things like: abs, min, max, etc..... > > for some code: > > int a; > > int food() > { > return abs(a); > } > > the corresponding operator should

...le.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, ValueType srcAType, > ValueType dstType, Operand ImmOd, ImmLeaf imm_type> > { > def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, > [(set dstReg:$dstD, (OpNode > srcAReg:$srcA))]>; > def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, >...

...UB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass srcBReg, RegisterClass dstReg, ValueType srcAType, ValueType srcBType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { .... def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx, [(directStore (dstType (OpNode imm_type:$srcA, (srcBType (load addr16:$srcB)))), addr16:$dstD)]...

...> On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >> Here is the instruction in question: >> >> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >> srcAReg, >> RegisterClass dstReg, ValueType srcAType, >> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >> { >> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >> [(set dstReg:$dstD, (OpNode >> srcAReg:$srcA))]>; >> def IMM_REG : SetADInOut<asms...

...10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >>> >>> Here is the instruction in question: >>> >>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>> srcAReg, >>> RegisterClass dstReg, ValueType srcAType, >>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>> { >>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>> [(set dstReg:$dstD, (OpNode >>> srcAReg:$srcA))]>; >>> def IMM_R...

...lt;ryta1203 at gmail.com> wrote: >>>> >>>> Here is the instruction in question: >>>> >>>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>>> srcAReg, >>>> RegisterClass dstReg, ValueType srcAType, >>>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>>> { >>>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>>> [(set dstReg:$dstD, (OpNode >>>> srcAReg:$srcA))]>; >&g...

Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the