Displaying 16 results from an estimated 16 matches for "srcregclass".
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setregclass
2011 Oct 06
4
[LLVMdev] Enhancing TableGen
...gt; For example, I want to be able to do this:
>
> defm MOVH :
> vs1x_fps_binary_vv_node_rmonly<
> 0x16, "movh", undef, 0,
> // rr
> [(undef)],
> // rm
> [(set DSTREGCLASS:$dst,
> (DSTTYPE (movlhps SRCREGCLASS:$src1,
> (DSTTYPE (bitconvert
> (v2f64 (scalar_to_vector
> (loadf64 addr:$src2))))))))],
> // rr Pat
> [],
> // rm Pat
&g...
2011 Oct 06
0
[LLVMdev] TableGen and Greenspun
...f
Pat<> patterns in a generic way?
For example, I want to be able to do this:
defm MOVH :
vs1x_fps_binary_vv_node_rmonly<
0x16, "movh", undef, 0,
// rr
[(undef)],
// rm
[(set DSTREGCLASS:$dst,
(DSTTYPE (movlhps SRCREGCLASS:$src1,
(DSTTYPE (bitconvert
(v2f64 (scalar_to_vector
(loadf64 addr:$src2))))))))],
// rr Pat
[],
// rm Pat
[[(DSTTYPE (mov...
2011 Oct 06
3
[LLVMdev] TableGen and Greenspun
The TableGen language seems to be growing Lisp macros from two different directions.
Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs.
It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like?
/jakob
2011 Oct 06
0
[LLVMdev] Enhancing TableGen
...o do this:
>>
>> defm MOVH :
>> vs1x_fps_binary_vv_node_rmonly<
>> 0x16, "movh", undef, 0,
>> // rr
>> [(undef)],
>> // rm
>> [(set DSTREGCLASS:$dst,
>> (DSTTYPE (movlhps SRCREGCLASS:$src1,
>> (DSTTYPE (bitconvert
>> (v2f64 (scalar_to_vector
>> (loadf64 addr:$src2))))))))],
>> // rr Pat
>> [],
>>...
2011 Oct 06
3
[LLVMdev] Enhancing TableGen
...>> defm MOVH :
>>> vs1x_fps_binary_vv_node_rmonly<
>>> 0x16, "movh", undef, 0,
>>> // rr
>>> [(undef)],
>>> // rm
>>> [(set DSTREGCLASS:$dst,
>>> (DSTTYPE (movlhps SRCREGCLASS:$src1,
>>> (DSTTYPE (bitconvert
>>> (v2f64 (scalar_to_vector
>>> (loadf64 addr:$src2))))))))],
>>> // rr Pat
>>>...
2009 May 15
1
[LLVMdev] RFC: More AVX Experience
...new
features in TableGen to facilitate writing generic patterns.
Here's an example:
//===----------------------------------------------------------------------===//
// Dummy defs for writing generic patterns
//===----------------------------------------------------------------------===//
def SRCREGCLASS;
def DSTREGCLASS;
def MEMCLASS;
def SRC1CLASS;
def SRC2CLASS;
def ADDRCLASS;
def INTRINSIC;
def TYPE;
def INTTYPE;
def MEMOP;
// TYPE - The data type (f32 for SS, f64 for SD, etc.)
// SRCREGCLASS - The source register class (VR128, FR32, etc.)
// DSTREGCLASS - The destination register class...
2009 Dec 03
2
[LLVMdev] Duplicate Label in Generates ISel
...GISel.inc:91442: error: previously used here
This seems to happen because of a pattern I added for VEXTRACTF128 which uses
extract_subreg:
[(set DSTREGCLASS:$dst,
(DSTTYPE (extract_subreg
(vector_shuffle
(SRCTYPE undef),
(SRCTYPE SRCREGCLASS:$src1),
VEXTRACTF128_shuffle_mask:$src2),
x86_subreg_128bit)))],
def x86_subreg_128bit : PatLeaf<(i32 1)>;
Curiously, I have analogous patterns for VINSERTF128 that use insert_subreg
but it doesn't generate any duplicate case values.
Anyone seen...
2011 Oct 06
4
[LLVMdev] TableGen and Greenspun
...r example, I want to be able to do this:
>
> defm MOVH :
> vs1x_fps_binary_vv_node_rmonly<
> 0x16, "movh", undef, 0,
> // rr
> [(undef)],
> // rm
> [(set DSTREGCLASS:$dst,
> (DSTTYPE (movlhps SRCREGCLASS:$src1,
> (DSTTYPE (bitconvert
> (v2f64 (scalar_to_vector
> (loadf64 addr:$src2))))))))],
> // rr Pat
> [],
> // rm...
2009 Dec 03
0
[LLVMdev] Duplicate Label in Generates ISel
...ere
>
> This seems to happen because of a pattern I added for VEXTRACTF128 which
> uses extract_subreg:
>
> [(set DSTREGCLASS:$dst,
> (DSTTYPE (extract_subreg
> (vector_shuffle
> (SRCTYPE undef),
> (SRCTYPE SRCREGCLASS:$src1),
> VEXTRACTF128_shuffle_mask:$src2),
> x86_subreg_128bit)))],
>
> def x86_subreg_128bit : PatLeaf<(i32 1)>;
Whoops, I forgot to fill in types:
(outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2)
[(set DSTREGCLASS:$dst,
(v4f3...
2009 Jun 15
2
[LLVMdev] Regular Expressions
...YPE,
!cast<ValueType>(!patsubst(".*ps$","v4f32",!patsubst(".*pd$","v2f64",OpcodeStr))),
To reduce redundancy, developers must be able to write generic patterns
like this:
[(set DSTREGCLASS:$dst, // rr, rrr
(xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))),
(INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))],
The substitution then fills in the appropriate types, etc. based
on which variant (32-bit, 64-bit, AVX, etc.) is being produced.
I suppose you could argue that additional parameters specifying
the source and dest types cou...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
...of
Pat<> patterns in a generic way?
For example, I want to be able to do this:
defm MOVH :
vs1x_fps_binary_vv_node_rmonly<
0x16, "movh", undef, 0,
// rr
[(undef)],
// rm
[(set DSTREGCLASS:$dst,
(DSTTYPE (movlhps SRCREGCLASS:$src1,
(DSTTYPE (bitconvert
(v2f64 (scalar_to_vector
(loadf64 addr:$src2))))))))],
// rr Pat
[],
// rm Pat
[[(DSTTYPE (mov...
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
...t;>> vs1x_fps_binary_vv_node_rmonly<
>>>> 0x16, "movh", undef, 0,
>>>> // rr
>>>> [(undef)],
>>>> // rm
>>>> [(set DSTREGCLASS:$dst,
>>>> (DSTTYPE (movlhps SRCREGCLASS:$src1,
>>>> (DSTTYPE (bitconvert
>>>> (v2f64 (scalar_to_vector
>>>> (loadf64 addr:$src2))))))))],
>>>> // rr Pat
&g...
2009 Dec 03
1
[LLVMdev] Duplicate Label in Generates ISel
...Greene wrote:
> Whoops, I forgot to fill in types:
>
> (outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2)
>
> [(set DSTREGCLASS:$dst,
> (v4f32 (extract_subreg
> (vector_shuffle
> (v8f32 undef),
> (v8f32 SRCREGCLASS:$src1),
> VEXTRACTF128_shuffle_mask:$src2),
> x86_subreg_128bit)))],
Well, it's conflicting with the hard-coded case statement from
DAGISelEmitter.cpp. What's the best way to resolve this? Introduce
another DAG operator that means the same thi...
2009 Jun 13
0
[LLVMdev] Regular Expressions
On Jun 11, 2009, at 2:01 PM, David Greene wrote:
> On Thursday 11 June 2009 12:28, Chris Lattner wrote:
>>>
>>> Yes. I want TableGen to be able to infer lots of stuff
>>> programmatically.
>>> This helps tremendously when specifying things like, oh, AVX. :)
>>
>> I don't see how this relates to regex's, and really don't want to
2009 Jun 15
0
[LLVMdev] Regular Expressions
On Jun 15, 2009, at 11:33 AM, David Greene wrote:
> To reduce redundancy, developers must be able to write generic
> patterns
> like this:
>
> [(set DSTREGCLASS:$dst, // rr, rrr
> (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))),
> (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))],
>
> The substitution then fills in the appropriate types, etc. based
> on which variant (32-bit, 64-bit, AVX, etc.) is being produced.
>
> I suppose you could argue that additional parameters specifying
&g...
2009 Jun 11
2
[LLVMdev] Regular Expressions
On Thursday 11 June 2009 12:28, Chris Lattner wrote:
> On Jun 9, 2009, at 12:39 PM, David Greene wrote:
> > On Tuesday 09 June 2009 14:34, Dan Gohman wrote:
> >> Can you describe what problem you're trying to solve here? Does it
> >> really need Regular Expressions?
> >
> > Yes. I want TableGen to be able to infer lots of stuff
> >