search for: setregclass

...o answer methods like getCommonSubClass(). In some cases it synthesizes new classes, which may or may not be allocatable depending on how the non-allocatable classes get mixed in. If a function like getCommonSubClass() returns a non-allocatable class, bad things happen (e.g. assertion failures from setRegClass()). It seems to me that functions like getCommonSubClass() should never return non-allocatable classes. But there seems to be no provision in tablegen to keep that from happening. It seems likely that no one has encountered this because for most targets non-allocatable classes contain registers th...

...RegClass. Anyway, if we cannot constrain VReg on DstRC (i.e., what we try in the previous if), this means that getCommonSubClass will fail or will return a class that is likely too small to be reasonable (i.e., below MinRCSize). Cheers, -Quentin > == DstRC) { > MRI->setRegClass(VReg, DstRC); > } > else { > BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), > TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); > VReg = NewVReg; > } > } > } > > This does not work. The logic seems...

...om> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); > else > BuildMI(... TargetOpcode::COPY...) > > The condition is trying to reset the reg class if the DstRC reg class is valid for the operand num of the machine instruction. If the NewVReg register class is not valid for that operand of the machine instruction I wan...

...we try in the >> previous if), this means that getCommonSubClass will fail or will return a >> class that is likely too small to be reasonable (i.e., below MinRCSize). >> >> Cheers, >> -Quentin >> >> >> == DstRC) { >> MRI->setRegClass(VReg, DstRC); >> } >> else { >> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >> TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); >> VReg = NewVReg; >> } >> } >> } >> >&g...

...onstrain VReg on DstRC (i.e., what we try in the previous if), this means that getCommonSubClass will fail or will return a class that is likely too small to be reasonable (i.e., below MinRCSize). > > Cheers, > -Quentin > > >> == DstRC) { >> MRI->setRegClass(VReg, DstRC); >> } >> else { >> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >> TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); >> VReg = NewVReg; >> } >> } >> } >> >&...

...w COPY? I admit I haven't thought this out but for my test cases so far this works just fine and reduces the number of ASM mov instructions that are being produced. > > For example, instead of BuildMI(..., TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg), use something like MRI->setRegClass(VReg, MRI->getRegClass(NewVReg)) ? The problem is that the old register class and the new one may not intersect. I do not know exactly what makes us create a new vreg w.r.t., but probably if the class is not identical we create one. You can try to use contraintsRegClass to get the intersection....

...gt;>>>>>> MinRCSize). >>>>>>> >>>>>>> Cheers, >>>>>>> -Quentin >>>>>>> >>>>>>> >>>>>>> == DstRC) { >>>>>>> MRI->setRegClass(VReg, DstRC); >>>>>>> } >>>>>>> else { >>>>>>> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >>>>>>> TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); >>>&...

...MinRCSize). >>>>>>>> >>>>>>>> Cheers, >>>>>>>> -Quentin >>>>>>>> >>>>>>>> >>>>>>>> == DstRC) { >>>>>>>> MRI->setRegClass(VReg, DstRC); >>>>>>>> } >>>>>>>> else { >>>>>>>> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >>>>>>>> TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg...

...>>>>> >>>>>>>>> Cheers, >>>>>>>>> -Quentin >>>>>>>>> >>>>>>>>> >>>>>>>>> == DstRC) { >>>>>>>>> MRI->setRegClass(VReg, DstRC); >>>>>>>>> } >>>>>>>>> else { >>>>>>>>> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >>>>>>>>> TII->get(TargetOpcode::COPY), NewV...

...;>>>>>>>>> Cheers, >>>>>>>>>> -Quentin >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> == DstRC) { >>>>>>>>>> MRI->setRegClass(VReg, DstRC); >>>>>>>>>> } >>>>>>>>>> else { >>>>>>>>>> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >>>>>>>>>> TII->get(TargetOpc...

...;>>>> Cheers, >>>>>>>>>>> -Quentin >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> == DstRC) { >>>>>>>>>>> MRI->setRegClass(VReg, DstRC); >>>>>>>>>>> } >>>>>>>>>>> else { >>>>>>>>>>> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >>>>>>>>>>> TII-&...

On Jan 7, 2011, at 11:25 AM, Dale Johannesen wrote: > We might want to make physical registers negative and virtuals positive, or vice versa. Then FirstVirtualRegister is 0 or 1, and we could get rid of those annoying subtractions of FirstVirtualRegister all over the virtual-register-handling passes. Since 0 is used all over the place as "invalid register" it is probably best to

Yes, you're probably right about the ID. The odd part is that I have other simpler instructions that use the same type of superset and it always, so far, matches correctly (it doesn't just pick GPRRegs all the time). Like I said, we can just 'fill in the gaps' with new MIs but that sure seems like a brush off solution. The td files would be so much cleaner if you could have a

...if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { > + const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); > + const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass); > + > + assert(newRegClass); > + > + MRI.setRegClass(MO.getReg(), newRegClass); > + } > + } > + } > +} > > Added: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h?rev=160270&view=auto > ========================================...