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Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.

..., > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU) > STORE dest_reg2, mem (functional unit: LOAD_STORE) > > These instructions can be genally packetized together because there is > no dependency among operands and they use different functional unit. But > we have one more restricton. The restriction...

...packetize instructions for VLIW at post-RA >>> stage or final codegen stage, where code transformations are not allowed >>> any more, because hardware can not resolve resource conflict. There is a >>> simple example as following: >>> >>> ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU) >>> STORE dest_reg2, mem (functional unit: LOAD_STORE) >>> >>> These instructions can be genally packetized together because there is >>> no dependency among operands and they use different functional unit. But >>> we h...

...-RA >>>>> stage or final codegen stage, where code transformations are not allowed >>>>> any more, because hardware can not resolve resource conflict. There is a >>>>> simple example as following: >>>>> >>>>> ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU) >>>>> STORE dest_reg2, mem (functional unit: LOAD_STORE) >>>>> >>>>> These instructions can be genally packetized together because there is >>>>> no dependency among operands and they use different functi...