search for: sra

I am trying to understand how LLVM does code generation and I have a couple of questions. I am using LLVM 2.6. First, if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, defm SRA : F3_12<"mysra", 0b100111, sra>; Is this correct? When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGen...

...e generation and I have a > > couple of questions. I am using LLVM 2.6. > > > > First, > > if I want to change the name of an instruction, all I need to do is to > > modify the XXXInstrInfo.td, right? Using Sparc as an example, if I > > wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would > > write, > > > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > > > Is this correct? > > Yes. IMHO, this is a poor way to do this kind of thing. It eventually leads to confusion wh...

...g to understand how LLVM does code generation and I have a couple of questions. > I am using LLVM 2.6. > > First, > if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? > Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > Is this correct? Yes. > When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "my...

LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. The library functions defined in RuntimeLibCalls.def (among others) are these: HANDLE_LIBCALL(SRA_I16, "__ashrhi3") HANDLE_LIBCALL(SRA_I32, "__ashrsi3") HANDLE_LIBCALL(SRA_I64, "__ashrdi3")...

...O_UNDEF and CTPOP. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev > Sent: Monday, June 10, 2019 8:31 AM > To: llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] [llvm-dev] Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL > > LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. > > The library functions defined in RuntimeLibCalls.def (among others) are these: > > HANDLE_LIBCALL(SRA_I16, &qu...

My target has only logical shifts and lacks an arithmetic right shift instruction. I have a custom LowerSRA function that rewrites SRA as SHL + SIGN_EXTEND when the shift width is either constant 16 or 24. Unfortunately, I observe that a later pass combines the SHL + SIGN_EXTEND back into SRA so we crash. The idea I had for defeating this behavior is lower to a target-specific version of SHL and/or SI...

...tNode(ISD::OR, dl, NVT, DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); return true; case ISD::SRA: // ShAmt < NVTBits Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. DAG.getConstant(NVTBits-1, ShTy)); Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. // ShAmt >= NVTBits Hi2 = DAG.getNode(ISD::SRA,...

...all. > > -Eli > > From: Joan Lluch <joan.lluch at icloud.com> > Sent: Monday, June 10, 2019 3:05 PM > To: Eli Friedman <efriedma at quicinc.com> > Cc: llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] Re: [llvm-dev] Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL > > Hi Eli, > > Thanks for pointing to the CTLZ_ZERO_UNDEF “LibCall” implementation. I have not it in the version that I am currently using, so it’s nice to know that it’s implemented now. > > Incidentally, the CTLZ… implementation is IDENTICAL to wh...

...(RdLo) asr r3, r2, #31 adc r1, r3, r1 (RdHi) ==> smlalbb r0, r1, r3, r2 I have added pattern in def SMLALBB : AMulxyI64< ..... as below :- [] modified to ---> [((set GPR:$RdLo, (ARMaddc (set GPR:$Rd, mul GPR:$Rn, GPR:$Rm), GPR:$RdLo)), (set GPR:$RdHi, (ARMadde (sra GPR:$Rd, (i32 31)), GPR:$RdHi, CPSR)))] This results in 'expected identifier in dag init' error. Obviously something is wrong in this pattern, I have not figured out what that is ? 2) ldrb r2, [r2] ldrb r3, [r3] smlal r0, r1, r3, r2 ==> smlalbb r0, r1, r3, r2 def : ARMV5MOPat&lt...

Hello LLVM, A recent commit creates the isIntDivCheap() target query. http://reviews.llvm.org/D12082 The current approach has a couple shortcomings. First, when targets decide divide is cheap, the DAGCombiner ignores obvious power-of-2 optimizations. In the targets I know, shifts are cheaper than divides in both speed and size. The target cannot see the value in the isIntDivCheap() call, so

...ome architecture. IR is as following. %cmp = icmp sgt <3 x i8> %x, zeroinitializer %sub = sub <3 x i8> zeroinitializer, %x %cond = select <3 x i1> %cmp, <3 x i8> %x, <3 x i8> %sub 'select' IR is converted to 'vselect' dag and is combined to 'sra (X, size(X)-1); xor (add (X, Y), Y)'. There is a problem here. If the target support i8 type as promote integer to make size(X), size(X) has i32 type. and then type legalize pass do widening the vector like this. v4i8 = BUILD_VECTOR 0x99d90a8: i32 = Constant<7> [ID=-3], 0x99d90a8: i32...

On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote: > Hello, > > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a

...  Optimized build.   Default target: x86_64-pc-linux-gnu   Host CPU: skylake ``` Thanks in advance Björn [1] http://blog.llvm.org/2011/11/llvm-30-type-system-rewrite.html -- Björn Fiedler, M.Sc. (Scientific Staff) Leibniz Universität Hannover (LUH) Fachgebiet System- und Rechnerarchitektur (SRA) Appelstraße 4 30167 Hannover, Germany Tel: +49 511 762-19736 Fax: +49 511 762-19733 eMail: fiedler at sra.uni-hannover.de WWW: https://www.sra.uni-hannover.de -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signat...

...owing. > > %cmp = icmp sgt <3 x i8> %x, zeroinitializer > %sub = sub <3 x i8> zeroinitializer, %x > %cond = select <3 x i1> %cmp, <3 x i8> %x, <3 x i8> %sub > > 'select' IR is converted to 'vselect' dag and is combined to 'sra (X, > size(X)-1); xor (add (X, Y), Y)'. There is a problem here. If the target support > i8 type as promote integer to make size(X), size(X) has i32 type. and then type > legalize pass do widening the vector like this. > > v4i8 = BUILD_VECTOR 0x99d90a8: i32 = Constant<7>...

...d that can make compiler co in loop or may end up generating wrong code. But I think SHL should be able to expanded to MUL and to prevent looping between MUL and SHL we can put a condition that only optimize MUL to SHL when SHL is not expanded operation. The similar logic can be applied to DIV and SRA. If there is any other reasons for not doing this, kindly explain. Sincerely, Vivek -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170303/6f0d0f16/attachment.html>

In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set

...: F3_12<"and" , 0b000001, and>; defm OR : F3_12<"or" , 0b000010, or>; defm XOR : F3_12<"xor" , 0b000011, xor>; defm SLL : F3_12<"sll" , 0b100101, shl>; defm SRL : F3_12<"srl" , 0b100110, srl>; defm SRA : F3_12<"sra" , 0b100111, sra>; defm ADD : F3_12<"add" , 0b000000, add>; defm ADDCC : F3_12<"addcc", 0b010000, addc>; defm ADDX : F3_12<"addx" , 0b001000, adde>; defm SUB : F3_12<"sub" , 0b000100, sub>; d...

...;> generating wrong code. >> >> But I think SHL should be able to expanded to MUL and to prevent looping >> between MUL and SHL we can put a condition that only optimize MUL to SHL >> when SHL is not expanded operation. The similar logic can be applied to DIV >> and SRA. >> >> If there is any other reasons for not doing this, kindly explain. >> >> Sincerely, >> Vivek >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> <javascript:_e(%7B...

...pass to the LEONPasses. (There is the Filler-pass, is this the right one?) --- Code example: clang compiles the following c-code: int main(void) { int *a = (int *) 0x80000000; int *b = (int *) 0x80000004; return *a / *b; } to [...] 49c: b5 3e 60 1f sra %i1, 0x1f, %i2 4a0: 81 80 00 1a wr %i2, %y 4a4: b0 7e 40 18 sdiv %i1, %i0, %i0 4a8: 81 c7 e0 08 ret gcc does: [...] 4a0: 87 38 60 1f sra %g1, 0x1f, %g3 4a4: 81 80 e0 00 wr %g3, %y 4a8: 01 00 00 00 nop 4ac: 01 00 00 00 nop 4b0:...

...by power of 2 already gets turned into a shift in instcombine; the tricky case is sdiv by power of 2, which takes significantly more than one instruction. The generic implementation is this: > > // Splat the sign bit into the register > SDValue SGN = > DAG.getNode(ISD::SRA, DL, VT, N0, > DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, > getShiftAmountTy(N0.getValueType()))); > AddToWorklist(SGN.getNode()); > > // Add (N0 < 0) ? abs2 - 1 : 0; > SDValue SRL = > DAG.ge...