search for: sram

...t (wide-band quality 8, complexity 1): - 162 MIPS with Analog-Devices lib - 128 MIPS with 1.2beta2 (faster but not working) I don't worry that much, as it's not the optimized version, and everything is running in SDRAM. Can you give me some advice on what I should try to put into internal SRAM ? Critical code ? Input samples ? Code-books ? Can we pre-allocate internal buffers heavily used by the encoder ? I'm also trying to compile Speex with asm optimizations. But it's targetted for GCC... I went through the archives, and found some entry-points to port asm-constraints to the...

...the 8kB of RAM that is always the same (lookup table etc.) or did you already think of that? I'm curios since the ATmega168 got 16kB of Flash that is as fast as the RAM (I think the chip is made so it limits its maximum speed to the slowest memory, flash. it also has some EEPROM besides the SRAM). //P?r Ps. ATmega spec: FLASH: 16kB EEPROM: 512B SRAM: 1kB SPEED: 0-20MHz Architecture: 8-bit RISC, no FPU. Site: http://www.atmel.com/dyn/products/product_card.asp?part_id=3303

...ough 3Ware's original FPGA ASIC designs in the AccelATA and Escalade 5000 series in 1999+. For a more "concept-level" dissertation on: - Software RAID via OS LDM/LVM - Fake/Free RAID (FRAID) "dumb cards" - Buffering Microcontroller+DRAM intelligent cards - Non-blocking ASIC+SRAM intelligent cards see my article "Dissecting ATA RAID Options in Sys Admin magazine (http://www.samag.com) 2004 April. It's now dated, but the concepts still apply. > One of my friends called me the other day regarding problems with centos > installation on 3ware 7810-8 controller....

Sorry for an OT post, but given the recent discussions here re raid, I was wondering if anyone had any info on the ITE 8212 RAID controller (GigaRAID) This is a PATA HW RAID as found on the GigaByte GA-8I915P-PRO motherboard. (I can see an IC on the board labeled GigaRAID. Their manual claims that is has it's own CPU). I am not using it because I have SATA, but I am still curious about

Thanks! The new are of xmega3 architecture, which is already included. So this should be simple. Where is the information about ISR-vector table, SRAM addresses and so on stored? -- Wilhelm Am 04.03.20 um 11:03 schrieb Dylan McKay: > Hey Wilhelm, > > This should be possible by editing the 'AVRDevices.td' [1]TableGen > definitions to add an entry for the newer chip types. You will need to > instruct LLVM which features ar...

Some things to check. Do you compile with VAR_ARRAYS? If not, you can probably reduce the size of the managed stack. In terms of data RAM, everything should fit into SRAM easily. I've done some massive wideband RAM reduction in 1.2beta2. If it's not working on Blackfin, then we'd need to investigate that first. Depending on whether you're using all the bit-rates, you might want to put only some of the codebooks in SRAM (if you tell me what bit-rate,...

...ave the encoder and decoder running now and have verified that the encoder is bit-exact wrt to the fixed-point code running on x86 for the same 30-second audio sample. Encode and decode together run in real-time for 8KHz data, complexity=3, on 120MHz C5509 when code and data are all in on-chip SRAM. I have not tested the wideband codec yet. >Here are a couple comments on the patch you sent (I looked at it, but >haven't compiled). > >1) The changes you made to the pack un unpack functions would only work >if the 16-bit chars are "big endian" (relative to the two...

...ReconRefFrames routine in hardware I will need at least 3 big buffers: Current Frame Last Frame Golden Frame On a 320x240 stream, it represent about 150 Kbyte of each buffer, so I will need about 500 Kbytes of memory. It is too much to use FPGA internal memory. So I'm planning use a external SRAM of 500Kbytes. SRAM data sheet: http://www.olimex.com/dev/pdf/71V416_DS_74666.pdf Another alternative is to use a PC100 SDRAM of 16 Mb: http://download.micron.com/pdf/datasheets/dram/sdram/128MbSDRAMx32.pdf http://www.altera.com/literature/ds/ds_sdram_ctrl.pdf My Altera Stratix Dev. Kit has this...

...currently 'translating' GNU assembly constraints to VDSP. I'm far from finished, but first attempts show no improvement over the C compiler. This is rather strange and would suggest memory bandwith limitation rather than code efficiency. I will investigate further by placing all in L1 SRAM. I'm using speex because of wide-band, and I'm pretty disapointed by performance considering it's slower than ADI's MP3 codec (10/20 MIPS for decoding/encoding of 44100 Hz @ 64 kbit/s). But maybe Jean-Marc would say the comparison is point-less ? Best regards. -- Stephane Les...

Am 04.03.20 um 11:16 schrieb Dylan McKay: > > The new are of xmega3 architecture, which is already included. So this > should be simple. > > Where is the information about ISR-vector table, SRAM addresses and so > on stored? > > > At the moment, this is not implemented in LLVM; these details are left > to the frontend. Clang/compiler-rt does not include the usual ISR table > or AVR-specific startup routines to initialize SRAM from program memory > - avr-clang-com...

Amit Ashara wrote: > 1. Since the stream I am working with is a mono channel, what should be > the advised page_segments to use. I am using an embedded system so > keeping the flash and SRAM usage are vital for the development. The number of channels has no impact on this at all. > 2. In the OpusTag the is the libopus a mandatory field? Yes.

Hi everyone, I'm looking into setting up a SATA hardware raid, probably 5 to use with CentOS 4. I chose hardware raid over software mostly because I like the fact that the raid is transparent to the OS. Does anyone know of any SATA controllers that are well tested for this sort of usage? From what I can tell from googling, this is more or less where RHEL stands: Red Hat Enterprise Linux

...ithout LINUX, we can't to use a .ogg file directly, we need to convert it in a vector and to compile with dump_video (the Leonardo also needs to do it on NIOS). http://www.students.ic.unicamp.br/~ra031198/theora_hardware/12_theora.png The next step will be to do plug it (the system [b]) on the SRAM memory in order to increase the resolution. The most important is that now we have a complete theora decoding on FPGA and with no NIOS or any module proprietary. Putting a ogg video a seeing a video on monitor! I had a lot of problems with LEON3 and the information about it is still very poor (t...

...And between biggish OSes for Blackfin the most popular choice is uCLinux. And ucLinux works best with gnu tools. Something like that. On the other hand, developers that use Blakfin in a manner similar to traditional 16-bit DSP usage model, i.e. without external RAM or with relatively small internal SRAM normally use no OS at all (like me) or ADI's VDK. These people naturally prefer ADI toolchain because it gives you good visibility of what's going on within a small "bare metal" target. But such developers a less likely to integrate speex because it simply doesn't fit. I gues...

...on in comments. I really have no idea of the performance difference on x86. But I think gcc/msvc can unroll. Up to you. Anyway I can OVERRIDE_INNER_PRODUCT_SINGLE. Talking about performance (still using generic version with VDSP compiler): 1. I got a pretty good boost by using a scratch buffer in SRAM. 2. Wideband Encode+Decode takes 79.1 + 7.2 MIPS on my BF536 400/133 Mhz 3. Profiler says: vq_nbest 33.05% vq_nbest_sign 11.12% filter_mem16 4.14% inner_prod 4.07% iir_mem16 2.75% qmf_synth 2.32% lsp_to_lpc...

...4, we're seeing significantly higher cycle counts -- more in the range of 100 MHz of CPU needed to encode with the same parameters. Additionally, compared to 1.0.3, the code size and data size of the Opus codec in 1.1 has increased significantly (which makes it a challenge to fit in the on-SoC SRAM of the M4). Obviously we need to use the ARM ASM that landed in -beta, and we can decrease the complexity to somewhat reduce the CPU utilization, but I'm wondering if I'm missing any other low-hanging fruit in optimizing Opus for this target CPU. I haven't even started to do code prof...

...ilt around an ARM microcontroller. I have seen other posts indicating that Speex can run in real-time on some iPAQ PDA's, but these are using a StrongARM 166MHz processor. I'm looking more at the chips from Atmel (SAM7), Philips (LPC2xxx), and TI (TMS 470), which are ARM7TDMI with on-chip SRAM and flash, running at speeds of 33 to 60MHz. 166 down to 60 is a big drop, but I'm hoping to gain performance due to lack of wait states (no external memory), and the lack of any O/S running to eat cycles; the chip will only be encoding Speex. Still, it may not be enough. Is it possible to p...

...decoder running now and have verified that the > encoder is bit-exact wrt to the fixed-point code running on x86 for the > same 30-second audio sample. Encode and decode together run in > real-time for 8KHz data, complexity=3, on 120MHz C5509 when code and > data are all in on-chip SRAM. I have not tested the wideband codec yet. Cool! Just curious, how much of the DSP does it take to do that? > I fixed the problem where extracting bytes from SpeexBits was wrong endian. Good! > I have not addressed this problem yet. In my testing all the Speex code > and data in the...

Hello Mailing List, I am a Speex supporter and user that would really like to know how much memory Speex uses to decode a 8kHz, 16kHz and 32kHz (primarily the 8kHz) and is it possible to use a 1kBytes of RAM to decode a 8kHz stream? (I was thinking of the possibility of using a ATmega168 to decode Speex) //P?r, Sweden

...0 bytes. Add the excitation memory and you've already blown the budget. > I'm curios since the > ATmega168 got 16kB of Flash that is as fast as the RAM (I think the chip > is made so it limits its maximum speed to the slowest memory, flash. it > also has some EEPROM besides the SRAM). It's not clear the code size + lookups would fit in the flash anyway. > Ps. ATmega spec: > FLASH: 16kB > EEPROM: 512B > SRAM: 1kB > SPEED: 0-20MHz Too slow. > Architecture: 8-bit RISC, no FPU. All the code assumes you have a 16x16 multiplier and a 32-bit accumulator. Em...