search for: sipi

...r (e.g. when going from UEFI to the OS). As a result, each layer that parks an AP must provide the physical address of an AP jump table to the next layer via the hypervisor. Upon booting of the kernel, read the AP jump table address from the hypervisor. Under SEV-ES, APs are started using the INIT-SIPI-SIPI sequence. Before issuing the first SIPI request for an AP, the start CS and IP is programmed into the AP jump table. Upon issuing the SIPI request, the AP will awaken and jump to that start CS:IP address. Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> [ jroedel at suse.de: - A...

On Tue, Apr 28, 2020 at 05:17:19PM +0200, Joerg Roedel wrote: > From: Tom Lendacky <thomas.lendacky at amd.com> > > Setup the AP jump table to point to the SEV-ES trampoline code so that > the APs can boot. Tom, in his laconic way, doesn't want to explain to us why is this even needed... :) /me reads the code /me reads the GHCB spec aha, it gets it from the HV. And it

From: Joerg Roedel <jroedel at suse.de> Add a play_dead handler when running under SEV-ES. This is needed because the hypervisor can't deliver an SIPI request to restart the AP. Instead the kernel has to issue a VMGEXIT to halt the VCPU. When the hypervisor would deliver and SIPI is wakes up the VCPU instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/include/uapi/asm/svm.h | 1 + arch/x86/kernel/sev-es.c | 58 +...

Cleanup vmx vmexit handler. Current code doesn''t handle vmexits caused by triple fault, INIT, SIPI, etc, which are listed in IA32 Architecture System Programming Guide 2, Appendix I VMX Basic Exit Reasons, and calls __hvm_bug() when not handling such cases, actually domain crash should be good enough. Also various coding style cleanups. Signed-off-by: Xin Li <xin.b.li@intel.com> _______...

Ladies, Gentlemen We are experiencing an unusual problem in our asterisk 1.4.34.. We are attempting to determine if channels are in use before paging to them. This works correctly, as in it pages the phone.. however, we see the error message below on the console... after googling, we discovered limited information regarding the issue... -- Executing [NPANXX7298 at from-pstn:1]

...by: Yongjie Ren <yongjie.ren@intel.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> changeset: 24447:a7b2610b8e5c user: Gang Wei <gang.wei@intel.com> date: Thu Dec 29 10:07:54 2011 +0000 X86: Add a delay between INIT & SIPIs for tboot AP bring-up in X2APIC case Without this delay, Xen could not bring APs up while working with TXT/tboot, because tboot needs some time in APs to handle INIT before becoming ready for receiving SIPIs (this delay was removed as part of c/s 23724 by Tim Deegan)....

Hello, XenServer has just had a support escalation, which resulted in this fix. It appears that certain Intel CPUs (X56xx series) with hyperthreading enabled have a race condition between an SMI (from the legacy USB support in this case) and an AP (the other hyperthread) between SIPI/INIT and trying to execute the first trampoline instruction. The race condition results in a CMCI complaining about a parity error in an instruction cache is delivered to Xen as soon as the SMI handler returns. On Xen-3.x, the CMCI handler dereferences the dom0 pointer, resulting in a pagefault at...

Hello, Has any more work been done on this front? The message below is from Sept. 2006. In particular, the LT/TXT Technology Enabling Platform (TEP) is now available from MPC Corp. Where can one obtain an appropriate AC SINIT module (i.e., like lpg_sinit_20050831_pae.auth.bin below)? I would like to begin using Xen with TXT support. Thanks, -Jon This patch adds SMP support to the

...Lendacky <thomas.lendacky at amd.com> Setup the AP jump table to point to the SEV-ES trampoline code so that the APs can boot. Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> [ jroedel at suse.de: - Adapted to different code base - Moved AP table setup from SIPI sending path to real-mode setup code - Fix sparse warnings ] Co-developed-by: Joerg Roedel <jroedel at suse.de> Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/include/asm/sev-es.h | 6 +++ arch/x86/include/uapi/asm/svm.h | 3 ++ arch/x86/kernel/sev-es.c...

From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build

...non SEV-ES guests too, so that it is less likely to break in the future. The other reason is that for SEV-ES guests the code needs to setup its own page-table to map the GHCB unencrypted. Without these patches the pre-decompression code only uses its own page-table when KASLR is enabled and used. SIPI and INIT Handling ---------------------- The hypervisor also can't make changes to the guest register state, which implies that it can't emulate SIPI and INIT messages. This means that any CPU register state reset needs to be done inside the guest. Most of this is handled in the firmware,...

...non SEV-ES guests too, so that it is less likely to break in the future. The other reason is that for SEV-ES guests the code needs to setup its own page-table to map the GHCB unencrypted. Without these patches the pre-decompression code only uses its own page-table when KASLR is enabled and used. SIPI and INIT Handling ---------------------- The hypervisor also can't make changes to the guest register state, which implies that it can't emulate SIPI and INIT messages. This means that any CPU register state reset needs to be done inside the guest. Most of this is handled in the firmware,...

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by