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Have not gotten much further on this, I can so far only use one memory with (for example) def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>; and def LDrr : F1< (outs GenRegs:$dst), (ins MEMrr:$addr), "ld*0* $dst, ($addr)",

Hello, My target has two data memories, each with its own load/store instructions but also has some instructions using both memories. I want to be able to access both memories in C-programs through the address space attribute. I have two ideas so far: Either: use two sets of addressing modes in InstrInfo.td: def ADDRrr_A : ComplexPattern<i16, 2, “SelectADDRrr_A", [], []>; def ADDRri :

...ntly does not support dereferencing 32-bit addresses in 64-bit mode. Specifically, addresses are defined as an iPTR type in X86InstrInfo.td which I assume is expanded to 4 or 8 bytes depending on if 32/64 bit mode is active: def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; The derefencing mov instruction looks like this: def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; So it expects a source address of type &...

...eferencing 32-bit > addresses in 64-bit mode. Specifically, addresses are defined as an > iPTR type in X86InstrInfo.td which I assume is expanded to 4 or 8 > bytes depending on if 32/64 bit mode is active: > def addr : ComplexPattern<iPTR, 5, "selectAddr", [], > [SDNPWantParent]>; > The derefencing mov instruction looks like this: > def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), > "mov{l}\t{$src, $dst|$dst, $src}", > [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; > So it expects a...

...coderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPRegs, GPRegs); let EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram $dst,$src", [(set GPRegs:$dst, (load addr:$src))]>; def STRAM : FG1<0b000010, (outs), (ins GPRegs:$src, mem:$dst), "stram $dst,$src", [(store GPRegs:$src, addr:$dst)]>; def ADD : FG2<0b000...

...: Pat<(i32 (extloadi16_a addr:$src)), (OR (LBu addr:$src), (SLL (LBu addr:($src+1)), 8))>; However, it failed to compiled. It seems that ($src+1) is a wrong representation in TableGen. I find the definition of adds: def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; How to calculate a new address in TableGen? Thanks, Yang

...(load ADDR_SHLI:$addr))], itin > { } The other related definitions are: // This class provides load/store address format selection support // class Addr< int numArgs, string funcName, dag opInfo > : Operand<i64>, ComplexPattern< i64, numArgs, funcName, [], [SDNPWantParent] > { let MIOperandInfo = opInfo; } let PrintMethod = "printMemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm",...

...: X86MemOperand<printMethod> { > let MIOperandInfo = (ops i8imm, RC, i32imm); > } > def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">; > > def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; > > class LD_INDIRECT_DESC_BASE2<string instr_asm, > RegisterOperand ROWD, > RegisterOperand ROWSP = ROWD, > InstrItinClass itin = NoItinerary> { >...

...ntMethod> : X86MemOperand<printMethod> { let MIOperandInfo = (ops i8imm, RC, i32imm); } def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">; def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; class LD_INDIRECT_DESC_BASE2<string instr_asm, RegisterOperand ROWD, RegisterOperand ROWSP = ROWD, InstrItinClass itin = NoItinerary> { dag OutOperandList...

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure: