Displaying 17 results from an estimated 17 matches for "sdnpoutglue".
2017 Sep 15
2
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...Start<[SDTCisVT<0, i32>, SDTCisVT<1,
i32>]>;
def SDT_MYCallSeqEnd : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1,
i32>]>;
def MYCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_MYCallSeqStart,
[SDNPHasChain, SDNPOutGlue]>;
def MYCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDT_MYCallSeqEnd,
[SDNPHasChain, SDNPOptInGlue,
SDNPOutGlue]>;
def SDT_MYCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def SDT_MYRet : SDTypeProfile<...
2017 Sep 15
0
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...i32>, SDTCisVT<1,
> i32>]>;
> def SDT_MYCallSeqEnd : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1,
> i32>]>;
> def MYCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_MYCallSeqStart,
> [SDNPHasChain, SDNPOutGlue]>;
> def MYCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDT_MYCallSeqEnd,
> [SDNPHasChain, SDNPOptInGlue,
> SDNPOutGlue]>;
>
> def SDT_MYCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
> def SDT_MYRe...
2017 Sep 19
1
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...’m missing something and can’t see what it is. I have simplified my TD description to just:
def MyCallseqStart : SDNode<"ISD::CALLSEQ_START",
SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>,
[SDNPHasChain, SDNPOutGlue]>;
def MyCallseqEnd : SDNode<"ISD::CALLSEQ_END",
SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
def my_call : SDNode<"MyISD::CALL",...
2016 Feb 02
2
New register class and patterns
...t; Let me clarify.
>
> I'm not sure I understand what you are saying. Let me post more information.
>
> Here is what I have defined for Escalasetflag
>
> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
> [SDNPOutGlue]>;
>
> How come it was working before and is is not working now? Clearly I'm missing something, but I can't figure out what.
>
> Any help is appreciated.
>
>
> --
> Rail Shafigulin
> Software Engineer
> Esencia Technologies
What is SDT_EscalaSetFlag?...
2019 Dec 10
3
Glue two instructions together
...REG:$r1),
(INST_OUT (INST_IN), REG:$r1)>;
where INST_IN doesn't accepts any inputs and INST_OUT accepts two inputs -
one returned by INST_IN and REG;$r1.
Is there any possibility to ‘Glue’ two instruction created in a such way?
Maybe something similar to creation SDNodes with SDNPOutGlue, SDNPInGlue) ?
These two instructions INST_IN and INST_OUT have to be one after another
without any other inserted between them.
Thanks,
Przemek
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2016 Feb 04
2
New register class and patterns
...M start complaining. Below I'm repeating some code for reference.
Any help is appreciated.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;...
2019 Dec 11
2
Glue two instructions together
...gt;> where INST_IN doesn't accepts any inputs and INST_OUT accepts two inputs - one returned by INST_IN and REG;$r1.
>>>
>>>
>>>
>>> Is there any possibility to ‘Glue’ two instruction created in a such way? Maybe something similar to creation SDNodes with SDNPOutGlue, SDNPInGlue) ?
>>>
>>>
>>>
>>> These two instructions INST_IN and INST_OUT have to be one after another without any other inserted between them.
>>>
>>>
>>>
>>> Thanks,
>>>
>>> Przemek
>
> ______________...
2016 Jan 29
3
New register class and patterns
On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote:
>
>>
>> Would anyone be able to figure out why this is happening? I can provide
>> more code if needed.
>>
>
> The error message should show what types have been inferred so far.
>
> You
2012 Jan 19
0
[LLVMdev] Problem generating <target>GenAsmMatcher.inc
...initions:
def SDT_MipsDivRem : SDTypeProfile<0, 2,
[SDTCisInt<0>,
SDTCisSameAs<0, 1>]>;
def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
[SDNPOutGlue]>;
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
RegisterClass RC, list<Register> DefRegs>:
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
[(op RC:$rs, RC:$rt)], itin>...
2013 Apr 15
3
[LLVMdev] Flag and Glue
My understand is that in DAG terminology, Flag is now called Glue.
It would be nice for someone to go through and clean up the code as far
as comments and variable names.
That was driving me close to the brink of insanity till I found out
about this.
Even in Selection Dag Node Properties
def SDNPOutGlue : SDNodeProperty; // Write a flag result
def SDNPInGlue : SDNodeProperty; // Read a flag operand
def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
2016 Feb 03
2
New register class and patterns
...t; I'm not sure I understand what you are saying. Let me post more
>> information.
>>
>> Here is what I have defined for Escalasetflag
>>
>> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
>> [SDNPOutGlue]>;
>>
>> How come it was working before and is is not working now? Clearly I'm
>> missing something, but I can't figure out what.
>>
>> Any help is appreciated.
>>
>>
>> --
>> Rail Shafigulin
>> Software Engineer
>> Esenci...
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...is appreciated.
========================= Orignal Code =====================================
def SDT_EsenciaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
def Esencia_CC_LT : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"...
2016 Jan 30
1
New register class and patterns
> On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
>
>
> I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf
2019 Jul 11
6
Glue to connect two nodes in LLVM backend
Hello everyone,
I wanted to attach a node without affecting the present nodes in any way. I
tried to use MVT::Glue for that but I think I'm missing something as I
could not achieve the below state.
LUI LUI
| |
ADDI ----GLUE---- ADDI
|
store
I've few question about this and Glue node in general, I'll be happy to get
some help on
2016 Feb 04
2
New register class and patterns
...aying that it sets a flag in the special purpose
register.
I'm reposting code for convenience.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
[SDNPOutGlue]>;
def Escala_CC_EQ : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETEQ);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),...
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
...[SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
+ def SDTSPeh_sjlj_setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
+ def SDTSPeh_sjlj_longjmp: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
+
def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
***************
*** 172,177 ****
--- 175,187 ----
def SPselectxcc : SDNode<"SPISD::SELECT_XCC", S...