search for: s17

...sp 80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def de...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...sp 80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def de...

...; works well and actually the interface with .C works OK. The question is that I can compile it in R, but ".Call" returns different result each time with same inputs. Could anybody tell me why? Thanks! Regards Shangru -- Department of Mathematics, National University of Singapore, Blk S17, 10 Lower Kent Ridge Road, 119076 [[alternative HTML version deleted]]

Hi, I am trying to read the "credit.lisp" file of the Japanese credit database in UCI repository, but it is in lisp format which I do not know how to read. I have not found how to do that in the foreign library http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening <http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening> Could anyone help me? Best

...en",main="For 10 million simulations") lines(myvalues_10M$num_sims_per_thread,myvalues_10M$time_per_sim,col="green") dev.off() print(paste("Plot was saved in:", getwd())) This generates a 3 page pdf file with a plot on each page. They look like this : http://s17.postimage.org/ud9ej1cnj/alpha1.png http://s13.postimage.org/7q3snqsrr/alpha2.png http://s14.postimage.org/sf374f12p/alpha3.png I want to plot all the 3 in one graph, in one page with the respective colours - red, blue, and green. Any ideas on how? Thanks, - vihan

...2006 S4 1 7.465 1/3/2006 S5 0 1.648 1/3/2006 S6 -1 5.36 1/3/2006 S7 -2 4.36 1/3/2006 S8 -3 3.574 1/3/2006 S9 -4 2.748 1/3/2006 S10 -5 1.933 1/3/2006 S11 -6 0.548 1/3/2006 S12 -7 -0.66 1/3/2006 S13 -8 -1.793 1/3/2006 S14 -9 -2.163 1/3/2006 S15 -10 -3.077 1/3/2006 S16 -11 -4.723 1/3/2006 S17 -12 -5.919 1/3/2006 S18 -13 -6.529 1/3/2006 S19 -14 -7.979 1/3/2006 S20 -15 -8.064 After making sure only positives are in for top 5 predictions and only negatives for the bottom 5 predictions 1/3/2006 S1 3 -1.943 1/3/2006 S20 4 10.376 1/3/2006 S3 2 8.611 1/3/2006 S4 1 7.465 1/3/2006 S16...

...so don't take my question as stopping the merge to head, I'm just making sure I got it right... The rest looks correct. + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, Does this mean that for floating point support in GHC, you need VFP registers? I don't know much how tablegen would work in this case, but I'd expect it to break during codegen (with a horrid error message) if you try to compile that to an ARMv4-ish...

...error: expected '{' at end of input make: *** [Projector2.o] Error 1 Warning message: running command 'R CMD SHLIB Projector2.c Projector.c' had status 1 What's the problem? Thanks all! Regards Li Shangru -- Department of Mathematics, National University of Singapore, Blk S17, 10 Lower Kent Ridge Road, 119076 [[alternative HTML version deleted]]

...3 8 S12 13 s 5 5 0 12 4 3 0 8 S13 14 s 5 6 4 9 4 6 2 6 S14 15 s 14 5 12 3 12 3 11 3 S15 16 s 7 2 11 3 5 2 10 2 S16 17 s 1 7 4 5 1 6 3 5 S17 18 s 6 2 7 4 6 2 7 4 S18 19 s 9 4 8 5 10 4 6 3 S19 20 s 8 2 6 5 9 2 6 4 S20 21 s 6 5 5 7 6 6 5 5 S21 22 s 8 8 3 7 6 7 5 3 S22 23 s...

Hello, first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. Anyway, I hope this is just a mistake or omission that such support was merged only into 3.0 and not also into HEAD. I've just found it by testing LLVM 3.1 with GHC 7.4.2 and

...f"), class = "factor"), site = structure(c(1L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, 21L, 12L, 5L, 7...

...t;Rf"), class = "factor"), site = structure(c(1L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, 21L, 12L, 5L, 7L),...

...;def>, %R7<def>, %R8<def>, %R9<def>, %R10<def>, %R11<def>, %PC<def> # End machine code for function test_kernel. *** Bad machine code: Using an undefined physical register *** - function: test_kernel - basic block: L.entry 0x1f65870 (BB#0) - instruction: %S17<def> = VMOVSR %R0<kill>, pred:14, pred:%noreg, %D8<imp-def>, %Q4<imp-use,kill>, %Q4<imp-def> - operand 5: %Q4<imp-use,kill> LLVM ERROR: Found 1 machine code errors. ________________________________________ De : Sebastien DELDON-GNB Date d'envoi : lundi 25...

...tor"), site = structure(c(1L, > > 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, > > 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", > > "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", > > "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, > > 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L...

Hi Anton, You're right it fails with a different message with llc 3.0. Anyway thanks for your help. Best Regards Seb > -----Original Message----- > From: Anton Korobeynikov [mailto:anton at korobeynikov.info] > Sent: Monday, June 25, 2012 3:39 PM > To: Sebastien DELDON-GNB > Cc: LLVMdev at cs.uiuc.edu; Rotem, Nadav > Subject: Re: RE : [LLVMdev] Is llc broken for Cortex-A9

...ot;), site = > structure(c(1L, > > 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, > > 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", > > "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", > > "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, > > 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L...

...05/2007 Randalstown 1 R5 FALSE 1 A 1 1 0 0 1 0 3 0 26.70 60 30/06/2007 Somerset 0 S14 FALSE 1 A 1 0 0 4 0 0 0 3 22.20 61 30/06/2007 Somerset 0 S15 FALSE 1 A 1 1 4 0 0 0 1 11 33.36 62 30/06/2007 Somerset 0 S17 FALSE 1 A 1 0 3 0 0 0 0 1 27.10 63 30/06/2007 Somerset 0 S2 FALSE 1 A 1 0 0 0 0 0 2 4 27.87 64 03/07/2007 Somerset 0 S25 FALSE 1 A 1 0 6 0 0 0 0 2 27.34 65 03/07/2007 Somerset 0 S28 FALSE 1 A 1 0...

...stion as stopping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, > + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, > > Does this mean that for floating point support in GHC, you need VFP registers? Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The code in GHC is pr...

...oved the type check on %1 entirely. This is safe for this particular rule since, by definition, G_ZEXT will always produce a larger scalar result type than its scalar input type and G_TRUNC will always produce a smaller one. The only way these can both be the case is if %1 is a a scalar of at least s17. We're still not covering every type combination that we ought to though since %S and %D are still restricted to s8 and s16 respectively. To fix this, we'll need some custom predicates. A custom predicate is declared like so: def isScalarType : GIMatchPredicate<(ins type:$A), bool,...