search for: rn

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2019 Sep 10
2
tablegen exponential behavior
Hi, I implemented a pattern matching of the dot product for arm64 and it seemed to work well for the basic case, i.e., class mulB<SDPatternOperator ldop> : PatFrag<(ops node:$Rn, node:$Rm, node:$offset), (mul (ldop (add node:$Rn, node:$offset)), (ldop (add node:$Rm, node:$offset)))>; cl...
2007 Aug 16
6
an easy way to construct this special matirx
Hi, Sorry if this is a repost. I searched but found no results. I am wondering if it is an easy way to construct the following matrix: r 1 0 0 0 r^2 r 1 0 0 r^3 r^2 r 1 0 r^4 r^3 r^2 r 1 where r could be any number. Thanks. Wen [[alternative HTML version deleted]]
2006 Jan 20
3
Troubles with the function rmultinom.c of the R's Random Number Generator
...Each loop of my Fortran calls the function rmultinom.c of the R's Random Number Generator through the wrapper: #include <R.h> #include <Rmath.h> void F77_SUB(sarmultinom)(int n, double* prob, int K, int* rN){ rmultinom(n, prob, K, rN);} My fortran program is: subroutine testsarmultinom(n,prob,K,rN) implicit none integer n,K,rN(K) double precision prob(K) call rndstart() call sarmultinom(n,prob,K,rN) call rndend() end In order to understand better how the function rmultinom.c works, I have writ...
2009 Nov 02
1
two small wishes (with code sugegstions) for R-core
Dear R developers, It would be great if you could implement the two minor code changes suggested below, which would help processing large objects in R. Jens Oehlschl?gel # Wish no. 1: let [.AsIs return the class AFTER subsetting, not the class of the original object # Wish no. 2: adjust write.csv and write.csv2 for multiple calls in chunked writing # Rationale no. 1: a couple of packages will return a different class than SomeClass when subsetting with [.SomeClass # and still need to keep the A...
2014 Mar 13
2
[LLVMdev] Be Careful with Positionally-Encoded Operands (AArch64, Mips, AMDGPU, etc.)
...; here's an example: > > > > AArch64 has the following instruction definition: > > > > SMULHxxx { > > field bits<32> Inst = { 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, Rm{4}, > > Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, Ra{4}, Ra{3}, Ra{2}, Ra{1}, > > Ra{0}, Rn{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{4}, Rd{3}, Rd{2}, > > Rd{1}, Rd{0} }; > > ... > > dag OutOperandList = (outs GPR64:$Rd); > > dag InOperandList = (ins GPR64:$Rn, GPR64:$Rm); > > string AsmString = "smulh $Rd, $Rn, $Rm"; > > list<dag>...
2014 Mar 13
5
[LLVMdev] Be Careful with Positionally-Encoded Operands (AArch64, Mips, AMDGPU, etc.)
...overlap with some of the named operands. I suspect this is not intentional; here's an example: AArch64 has the following instruction definition: SMULHxxx { field bits<32> Inst = { 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, Rm{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, Ra{4}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rn{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{4}, Rd{3}, Rd{2}, Rd{1}, Rd{0} }; ... dag OutOperandList = (outs GPR64:$Rd); dag InOperandList = (ins GPR64:$Rn, GPR64:$Rm); string AsmString = "smulh $Rd, $Rn, $Rm"; list<dag> Pattern = [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))]; ......
2011 Apr 28
1
Trying to perform an inner loop a random number of times
Grateful for any hints as to why I'm not getting the inner loop to cycle the expected number of times. Code and one run's results below. Thanks, Galen > # source("looptest.r") > sp<-numeric() > iter<-numeric() > rn<-numeric() > ds<-data.frame(sp, iter, rn) > > for (sp in c(1:6)) { + i<-1 + while (i <= 5) { + rn<-0 + rn<-round(runif(1, 1, 5)) + if (i > rn) { break } + +...
2007 May 21
1
[LLVMdev] instruction writing two successive registers
hi, the architecture that we are compiling for has a special vector shuffle instruction, which writes two successive registers (Rn and Rn+1). i have defined intrinsics to generate the instruction, and a special register class for the register pairs. in addition i have two EXTRACT operations which allow to access either the first or second subregister of a pair (using moves). the pair register class is used only for this purpo...
2012 Jul 11
2
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
Hello, FYI, this is a bug http://llvm.org/bugs/show_bug.cgi?id=13324 When compiling the following code for sm_20, func params are by some reason given with .align 0, which is invalid. Problem does not occur if compiled for sm_10. > cat test.ll ; ModuleID = '__kernelgen_main_module' target datalayout = "e-p:64:64-i64:64:64-f64:64:64-n1:8:16:32:64" target triple = "ptx64-unknown-unknown" %struct.float2 = type { float, float } define ptx_device void @__internal_dsmul(%struct.float2* noalias nocapture sret %agg.result, %struct.float2* n...
2012 Jul 10
1
Why 95% "quantile" empty in R or why 95% "quantile" = 1 with data values between 0 and 1?
I am calling quantiles as follows. I don't understand why sometimes the columns (data values) above 95% are returned as "NULL"!! When I drop the percentile down to 92%, I see colums appearing. Why would any quantile be empty? I see sometimes that 95% percentile is being chosen as "1" for my data between 0 and 1, where obviously there's no column value equal to 1. But why would 95% of a d...
2015 Sep 15
2
Parsing Operands at TableGen Level
Hi all, is it possible in TableGen to set value to instruction bits based on the operands? In other words, parsing the instruction at the TableGen level. for instance: "add $Rd, $Rn, $imm" I want to have something like this: *Inst{8} = ($Rn == Test::A0) 1 : 0;* Is there any way to do that in TableGen? If not is there any example in the provided example codes? Cheers, ES -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.l...
2015 Jun 27
2
[LLVMdev] readonly and infinite loops
Running -early-cse on declare void @rn() readnone nounwind define void @f() { entry: call void @rn() ret void } removes the call to @rn(). But @rn() could have had an infinite loop in it in which case @f() went from being a non-terminating program to an terminating no-op. Is this intentional? The only way I can see this transf...
2016 Mar 18
2
Incoming INVITE with Portability Info and LRN
On Fri, Mar 18, 2016 at 10:49 AM Administrator TOOTAI <admin at tootai.net> wrote: > Le 18/03/2016 16:20, Trey Hilyard a ?crit : > > I am trying to set up my Asterisk server so that it will recognize an > > incoming call to the Asterisk's own Location Routing Number (LRN), > > validating the "rn" in the INVITE and then using the Called Number from > > the INVITE as the extension in the dialplan. > > > > The INVITE R-URI looks like: > > INVITE > > sip:+19135041291;rn=+19136630000;npdi at 12.4.240.200 > :5060;user=phon...
2011 May 27
1
How to convert an ftable object to a matrix including the row names?
...to do it... Cheers, Marius ## Goal: convert an ftable() to a (character) matrix including the row names of ## the ftable object as columns in the matrix (so that the matrix can be ## nicely printed with xtable() for example) (ft <- ftable(Titanic, row.vars=1:3)) # ftable object rn <- attr(ft, "row.vars") # pick out rownames rn. <- rn[length(rn):1] # unfortunately, we have to (?) change the order due to expand.grid() g <- expand.grid(rn.) # build the 3 columns containing the row names (g. <- g[,length(rn):1]) # change order back; now contains the same ro...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
Hi, We're having an issue with TailDuplication in our out-of-tree target and it's this PHI-node that seems to be the cause of the trouble: %vreg2<def> = PHI %vreg0, <BB#2>, %vreg1, <BB#3>; rN:%vreg2 aNlh_0_7:%vreg0 aNlh_rN:%vreg1 Note that the defined %vreg2 has register class "rN" while the read %vreg0 has register class "aNlh_0_7". "rN" and "aNlh_0_7" are disjoint. Is such a PHI node ok? If it is, then there is a bug in TailDuplication. Be...
2006 Jan 22
0
IP SIP Phone/2.0.6
...problem before. Thanks for your anticipated help. Cheers, Richard Here is a snippet from the debug log; asterisk1*CLI> <-- SIP read from 82.35.xxx.23:33344: REGISTER sip:xxx.xxx.xxx.xxx SIP/2.0 Content-Length: 0 Via: SIP/2.0/UDP 82.35.xxx.23:33344;branch=z9hG4bK21852074 To: "RN SYSTEMS LTD" <sip:119@ pbx.sytes.net > From: "RN SYSTEMS LTD" <sip:119@pbx.sytes.net>;tag=22d32002 Call-ID: 0a4132dc-44a3276f-8d5e4f44-bc07bcd5@192.168.1.3 CSeq: 2230 REGISTER Expires: 30 User-Agent: IP SIP Phone/2.0.6 Max-Forwards: 70 Contact: <sip:119@82.35.xx...
2009 Mar 09
2
bug of *switch* function
...I use is R version 2.9.0 Under development (unstable) (2009-02-21 r47969) here is the output: > organism="human" > species <- switch(organism, human <- "Hs", fly <- "Dm", mouse <- "Mm", rat <- "Rn", yeast <- "Sc" ) species <- switch(organism, + human <- "Hs", + fly <- "Dm", + mouse <- "Mm", + rat <- "Rn", + yeast <- "Sc" + ) > species [1] "Hs" > organism="yeast&q...
2015 Jun 27
4
[LLVMdev] readonly and infinite loops
...rminate. It would probably fine for > readonly functions as well. > > Nuno > > > -----Original Message----- > From: Sanjoy Das > Sent: Saturday, June 27, 2015 9:29 PM > Subject: [LLVMdev] readonly and infinite loops > > Running -early-cse on > > declare void @rn() readnone nounwind > > define void @f() { > entry: > call void @rn() > ret void > } > > removes the call to @rn(). But @rn() could have had an infinite loop > in it in which case @f() went from being a non-terminating > program to an terminating no-op. Is this int...
2012 Nov 09
0
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
...GVar->getAlignment(); Could you please review and commit? Do you think it needs a test case? Thanks, - D. dmikushin at hp2:~/forge/align0> llc -march=nvptx64 -mcpu=sm_20 align0.ll -o - // // Generated by LLVM NVPTX Back-End // .version 3.1 .target sm_20 .address_size 64 // .globl __internal_dsmul .visible .func __internal_dsmul( .param .b64 __internal_dsmul_param_0, .param .align 4 .b8 __internal_dsmul_param_1[8], .param .align 4 .b8 __internal_dsmul_param_2[8] ) // @__internal_dsmul { .reg .pred %p<396>; .reg .s16 %rc<396>; .r...
2016 Mar 18
2
Incoming INVITE with Portability Info and LRN
I am trying to set up my Asterisk server so that it will recognize an incoming call to the Asterisk's own Location Routing Number (LRN), validating the "rn" in the INVITE and then using the Called Number from the INVITE as the extension in the dialplan. The INVITE R-URI looks like: INVITE sip:+19135041291;rn=+19136630000;npdi at 12.4.240.200:5060;user=phone;transport=udp SIP/2.0 The +1913663000 is the LRN of the Asteri...