llvm dev - Sep 2015 - Parsing Operands at TableGen Level

Hi all,

is it possible in TableGen to set value to instruction bits based on the
operands?
In other words, parsing the instruction at the TableGen level.

for instance:

"add $Rd, $Rn, $imm"

I want to have something like this:

*Inst{8} = ($Rn == Test::A0)  1 : 0;*

Is there any way to do that in TableGen? If not is there any example in the
provided example codes?

Cheers,
ES
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On Tue, Sep 15, 2015 at 04:15:32PM +0200, Sky Flyer via llvm-dev
wrote:
> Hi all,
> 
> is it possible in TableGen to set value to instruction bits based on the
> operands?
> In other words, parsing the instruction at the TableGen level.
> 
> for instance:
> 
> "add $Rd, $Rn, $imm"
> 
> I want to have something like this:
> 
> *Inst{8} = ($Rn == Test::A0)  1 : 0;*
> 
One solution to this is to add extra bits to the register encoding.  Here is
a pseudo code example if you have 8-bit register encoding:

class ARegister : Register <string Name, bits<16> enc> : Register
<name> {
  let HWEncoding = enc;
}

def A0 : ARegister <"A0", 0x100>
def A1 : ARegister <"A1", 0x001>
def A2 : ARegister <"A2", 0x002>

...

class InstFormat {

  bits<9> Rn;

  Inst{7-0} = Rn{7-0};
  Inst{8} = Rn{8}

}

-Tom

> Is there any way to do that in TableGen? If not is there any example in the
> provided example codes?
> 
> Cheers,
> ES
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

That really helped!
Thanks a lot.

On Tue, Sep 15, 2015 at 4:51 PM, Tom Stellard <tom at stellard.net> wrote:
> On Tue, Sep 15, 2015 at 04:15:32PM +0200, Sky Flyer via llvm-dev wrote:
> > Hi all,
> >
> > is it possible in TableGen to set value to instruction bits based on
the
> > operands?
> > In other words, parsing the instruction at the TableGen level.
> >
> > for instance:
> >
> > "add $Rd, $Rn, $imm"
> >
> > I want to have something like this:
> >
> > *Inst{8} = ($Rn == Test::A0)  1 : 0;*
> >
>
> One solution to this is to add extra bits to the register encoding.  Here
> is
> a pseudo code example if you have 8-bit register encoding:
>
> class ARegister : Register <string Name, bits<16> enc> :
Register <name> {
>   let HWEncoding = enc;
> }
>
> def A0 : ARegister <"A0", 0x100>
> def A1 : ARegister <"A1", 0x001>
> def A2 : ARegister <"A2", 0x002>
>
> ...
>
> class InstFormat {
>
>   bits<9> Rn;
>
>   Inst{7-0} = Rn{7-0};
>   Inst{8} = Rn{8}
>
> }
>
> -Tom
>
>
> > Is there any way to do that in TableGen? If not is there any example
in
> the
> > provided example codes?
> >
> > Cheers,
> > ES
>
> > _______________________________________________
> > LLVM Developers mailing list
> > llvm-dev at lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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