search for: registersdnod

Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? More Specifically: SDValue Reg3 = Node->getOperand(3); if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) { op3 = cast<RegisterSDNode>(Reg3)->getReg(); fprintf(stderr,"Op3 is register and regnum is %d\n",op3); } else if (ConstantSDNod...

...1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? > > More Specifically: > SDValue Reg3 = Node->getOperand(3); > if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) > { > op3 = cast<RegisterSDNode>(Reg3)->getReg(); > fprintf(stderr,"Op3 is register and regnum is %d\n",op3); > } >...

...bujbwt at gmail.com> wrote: > > > > Is it possible to get a register number to which the value is allocated > to in MIPS in DAGToDAG class? > > > > More Specifically: > > SDValue Reg3 = Node->getOperand(3); > > if (RegisterSDNode *R = > dyn_cast<RegisterSDNode>(Reg3)) > > { > > op3 = cast<RegisterSDNode>(Reg3)->getReg(); > > fprintf(stderr,"Op3 is register and regnum is > %d\n",op3); > >...

Hello everybody, hi Evan, this patch changes the lowering of arguments for tail call optimized calls. Before arguments that could be overwritten by each other were explicitly lowered to a stack slot, not giving the register allocator a chance to optimize. Now a sequence of copyto/copyfrom virtual registers ensures that arguments are loaded in (virtual) registers before they are lowered to the

...!IsClone && !IsCloned)        for (SDNode *User : Node->uses()) {          if (User->getOpcode() == ISD::CopyToReg &&              User->getOperand(2).getNode() == Node &&              User->getOperand(2).getResNo() == i) {            unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();            if (TargetRegisterInfo::isVirtualRegister(Reg)) { -            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); -            if (RegRC == RC) { +            // Allow constraining the virtual register's class within reason, +   ...

...n't behave // like other nodes from the perspective of scheduling heuristics. - if (SDNode *N = SU->getNode()) + if (SDNode *N = PredSU->getNode()) if (N->getOpcode() == ISD::CopyFromReg && TargetRegisterInfo::isVirtualRegister (cast<RegisterSDNode>(N->getOperand(1))->getReg())) ~ -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130821/721dc102/attachment.html>

On Thu, Feb 18, 2016 at 11:34 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:32 PM, Rail Shafigulin wrote: > >> I think this is where I'm loosing the "thread". Based on what I'm seeing >> SET_FLAG has three operands, the first of which is a CopyFromReg. So how >> come the pattern is SET_FLAG %vreg5, 3, 20 and not

...e it in an unusual way. Please contact the application's support team for more information. Assertation failed! Program: C:\Developer\Mingw-NG\home\Vincent\llvm-2.7\Release\bin\clang.exe File: X86ISelLowering.cpp, Line 2152 Expression: ((Callee.getOpcode() == ISD::Register && (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX || cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress) && "Expec clang: error: compiler command failed with exit code 3 (use -v to see i...

...uring Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem seems to be that somehow the CopyToReg part of the switch statement in ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is especially problematic because the code is either expecting a VirtualRegister or a RegisterSDNode in this location. I've checked all locations where I use the DAG.getCopyToReg function and none of them pass in a frameindex. I explcitily check that I have a register before passing in the value to Register number to CopyToReg, so this leads me to believe that it is being generated somehow by...

...edule() in SelectionDAGISel.cpp:695. The problem > seems > to be that somehow the CopyToReg part of the switch statement in > ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is > especially problematic because the code is either expecting a > VirtualRegister or a RegisterSDNode in this location. I've checked all Unfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan > > locations where I use the DAG.getCopyT...

...d.s In addition, passive nodes are omitted from scheduled during instruction scheduling such that they are free to be placed anywhere while generating the instruction sequence. Is this related with above problem of debug location ? The list of passive nodes are :- ConstantSDNode ConstantFPSDNode RegisterSDNode RegisterMaskSDNode GlobalAddressSDNode BasicBlockSDNode FrameIndexSDNode ConstantPoolSDNode JumpTableSDNode ExternalSymbolSDNode BlockAddressSDNode MDNodeSDNode Thanks Karthik -------------- next part -------------- A non-text attachment was scrubbed... Name: gdb11531.s Type: application/octet...

...stCallTailCall) { + IsLastCallTailCall = false; + SDOperand TailCall = GetTailCall(Op); + SDOperand TargetAddress = TailCall.getOperand(1); + SDOperand StackAdjustment = TailCall.getOperand(2); + assert ( ((TargetAddress.getOpcode() == ISD::Register && + cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX) || + TargetAddress.getOpcode() == ISD::TargetExternalSymbol || + TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && + "Expecting an global address, external symbol, or register"); + a...

...o > /// set to this value, and a value. > CopyToReg, > > /// CopyFromReg - This node indicates that the input value is a > virtual or > /// physical register that is defined outside of the scope of this > /// SelectionDAG. The register is available from the RegisterSDNode > object. > CopyFromReg, > > I usually grep the sources if I want to find out about something. I'm not > sure if there is a better documentation about ISD nodes. Thanks. I keep forgetting that I have grep at my disposal :) What I'm not clear about is the first paramet...

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

On Mon, Jun 6, 2016 at 8:32 AM, Nemanja Ivanovic via llvm-dev <llvm-dev at lists.llvm.org> wrote: > It is not a keyword. It is a node defined in > include/llvm/Target/TargetSelectionDAG.td. You can likely find most of the > definitions you're wondering about there. > In terms of its purpose, perhaps someone can elaborate on that a bit more, > but there is no corresponding

Other than not using debugging ('-g' and the like), not really. :-( I think that Devang is actively working on fixing this, though. It might not be too much longer. -bw On Thu, Jan 15, 2009 at 3:26 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > This did not seem to work, any other ideas? > > Thanks, > > -----Original Message----- > From: llvmdev-bounces at

...edule() in SelectionDAGISel.cpp:695. The problem > seems > to be that somehow the CopyToReg part of the switch statement in > ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is > especially problematic because the code is either expecting a > VirtualRegister or a RegisterSDNode in this location. I've checked all Unfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan > > locations where I use the DAG.getCopyT...

...LastCallTailCall = false; > + SDOperand TailCall = GetTailCall(Op); > + SDOperand TargetAddress = TailCall.getOperand(1); > + SDOperand StackAdjustment = TailCall.getOperand(2); > + assert ( ((TargetAddress.getOpcode() == ISD::Register && > + cast<RegisterSDNode>(TargetAddress)->getReg() == > X86::ECX) || > + TargetAddress.getOpcode() == > ISD::TargetExternalSymbol || > + TargetAddress.getOpcode() == > ISD::TargetGlobalAddress) && > + "Expecting an global address, external symb...

This did not seem to work, any other ideas? Thanks, -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Bill Wendling Sent: Thursday, January 15, 2009 2:26 PM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Hitting assertion, unsure why Don't generate debug info at this time (you can use "opt -strip-debug")?