Displaying 20 results from an estimated 273 matches for "registerclasses".
2013 Jun 25
2
[LLVMdev] Adding a new ARM RegisterClass
I'm looking at an issue where we want a particular pseudo-instruction to
choose from a set of registers that is not included in the existing set of
RegisterClass definitions. More concretely, there is a RegisterClass in
ARMRegisterInfo.td defined as
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
Hi, everyone.
I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def ReadOnlyRegClass : RegisterClass<...>;
def GeneralPurposeRegClass : RegisterClass<...>;...
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...isha Brukman <brukman at cs.uiuc.edu>:
> On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
> > I' have three set of registers - read-only regs, general purpose regs
> > (read and write), and write-only regs. How should I partition them
> > into different RegisterClasses so that I can easy define the
> > instruction?
> [snip]
> > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
> > GeneralPurposeRegClass :$src), "mov $dest, $src">;
> >
> > There can be only one RegisterClass defined for each instructio...
2019 Jul 18
2
Question about TableGen RegisterClass definition
Hi All,
I have a question about TableGen RegisterClass definition.
I need to map different size of MVTs into a register class as below.
def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>
When I look at TableGen and CodeGen, it looks the types are used as following:
1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction
2018 Apr 12
0
How to specify the RegisterClass of an IMPLICIT_DEF?
On 4/12/2018 8:01 AM, Dominique Torette via llvm-dev wrote:
>
> But there is one small issue in the inference of RegisterClass of the
> implicitly defined register.
>
> As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass.
>
> This register class accepts the v2f32 type, but for others addressing
> mode context this register should be
2016 Jan 07
3
BPF backend with vector operations - some strange error
Hello.
I've tried to add some simple arithmetic vector operations to the BPF backend
available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass
(taken from the Mips backend):
def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128,
(sequence "W%u", 0, 31)>;
in order to support vector for example, ADD
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
> I' have three set of registers - read-only regs, general purpose regs
> (read and write), and write-only regs. How should I partition them
> into different RegisterClasses so that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
> GeneralPurposeRegClass :$src), "mov $dest, $src">;
>
> There can be only one RegisterClass defined for each instruction
> operand, but actually...
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace =
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...<brukman at cs.uiuc.edu>:
>> On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
>>> I' have three set of registers - read-only regs, general purpose regs
>>> (read and write), and write-only regs. How should I partition them
>>> into different RegisterClasses so that I can easy define the
>>> instruction?
>> [snip]
>>> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>>> GeneralPurposeRegClass :$src), "mov $dest, $src">;
>>>
>>> There can be only one RegisterClass defined...
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote:
> 2005/7/23, Chris Lattner <sabre at nondot.org>:
>> What does a 'read only' register mean? Is it a constant (e.g. returns
>> 1.0)? Otherwise, how can it be a useful value?
>
> Yes, it's a constant register.
>
> Because the instruction cannot contain an immediate value, a constant
> value may be stored in
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
Hi,
I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture.
def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)),
(INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),
2014 Jan 19
2
[LLVMdev] Why make the register list a dag for RegisterClass in target descriptor file?
The blow snippet in target.td shows the regList in RegisterClass is typed
as dag. Why not make it a simple list, such as list<Register>?
class RegisterClass<string namespace,
list<ValueType> regTypes, int alignment, dag regList>
Thanks,
-Thomson
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2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
I'm not at the machine that has the changes, but it was failing at index 0.
Micah
From: Owen Anderson [mailto:resistor at mac.com]
Sent: Thursday, April 19, 2012 3:35 PM
To: Villmow, Micah
Cc: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
Thanks, I think it can solve my problem.
But please allow me to explain the hardware in detail. Hope there is
more elegant way to solve it.
The hardware is a "stream processor". That is, It processes samples
one by one. Each sample is associated with several 128-bit
four-element vector registers, namely:
* input registers - the attributes of the sample, the values of the
registers
2006 May 13
2
[LLVMdev] TableGen: RegisterClass question
Hi,
I'm porting some existing code of mine to CVS HEAD, and don't understand
something about new RegisterClass TableGen definition:
class RegisterClass<string namespace, list<ValueType> regTypes,........
{
.....
string Namespace = namespace;
What is this "namespace" thing? It looks like it should contain the name of
backend, right?
// RegType
2007 Feb 12
2
[LLVMdev] bitconvert for multi-typed RegisterClasses
...vert (type1 MR:$src))), (type2 MR:$src)>;
...
Adding these patterns appeared to allow the instruction selector to
select/legalize the store operations. So I have two questions:
1) Is relying on these patterns for instruction selection/
legalization the correct way to implement multi-typed
RegisterClasses? I like having TableGen do the pattern work for me
rather than writing custom selection code...
2) I'd think that when a multi-typed RegisterClass is declared that
these bitconvert patterns between types in that class automatically
become legal. Is there a reason that TableGen shouldn...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate?
-Owen
On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> I am trying to make
2005 Jul 25
1
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/24, Chris Lattner <sabre at nondot.org>:
> Ah, ok. In that case, you want to put all of the registers in one register
> file, and not make the constant register allocatable (e.g. see
> X86RegisterInfo.td, and note how the register classes include EBP and ESP,
> but do not register allocate them (through the definition of
> allocation_order_end()).
>
> -Chris
2005 Jul 26
0
[LLVMdev] How to partition registers into different RegisterClass?
On Mon, 25 Jul 2005, Tzu-Chien Chiu wrote:
> But please allow me to explain the hardware in detail. Hope there is
> more elegant way to solve it.
Sounds good!
> The hardware is a "stream processor". That is, It processes samples
> one by one. Each sample is associated with several 128-bit
> four-element vector registers, namely:
>
> * input registers - the