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...t;addSuccessor(MBB_cond); MBB_cond->addSuccessor(MBB_erase); MBB_cond->addSuccessor(MBB_end); MBB_erase->addSuccessor(MBB_cond); MBB_erase->addSuccessor(MBB_end); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); unsigned regA = MRI.createVirtualRegister(AddrRegClass); unsigned regB = MRI.createVirtualRegister(AddrRegClass); unsigned regC = MRI.createVirtualRegister(AddrRegClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(r...

...final regression discovered when upgrading XenServer from Xen 4.1 to 4.3, there is an issue with RTC emulation. Win2003 SP2 is a WAET unaware operating system, whose RTC access pattern triggers Xen''s rtc_mode_no_ack logic. The result is that the domain falls into a tight loop reading RTC RegC, whoes value is always 0xc0. I have confirmed that switching Xen back to RTC strict mode fixes the regression, but I am presuming that this alone would be an unpopular fix upstream. At the moment, HVMloader unconditionally advertises the RTC_NO_ACK bit in the WAET table, and Xen unconditionally d...

Hi, I can't find a way to define a subregister in a MI, while using another subregister in the same MI. For example: reg:low = OP reg:hi, rhs I really need the reg:low to be part of the same register as reg:hi, but when I use REG_SEQUENCE, this does not happen - I instead get regC = OP reg:hi, rhs reg:low = regC This is not good enough for me. What should I do? /Jonas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111109/a9faf148/attachment.html>

...ccessor(MBB_erase); >> MBB_cond->addSuccessor(MBB_end); >> MBB_erase->addSuccessor(MBB_cond); >> MBB_erase->addSuccessor(MBB_end); >> >> MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); >> const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); >> unsigned regA = MRI.createVirtualRegister(AddrRegClass); >> unsigned regB = MRI.createVirtualRegister(AddrRegClass); >> unsigned regC = MRI.createVirtualRegister(AddrRegClass); >> >> // Set the indice >> BuildMI(*...

...<DoAction> + <actions> + <PushData> + <items> + <StackString value="Check how DefineFunction2 handles register counts"/> + </items> + </PushData> + <Trace/> + <DeclareFunction2 name="foo" argc="0" regc="0"> + <actions> + <PushData> + <items> + <StackString value="hi"/> + </items> + </PushData> + <StoreRegister reg="0"/> + <StoreRegister reg="1"/> +...

...on> + <actions> + <PushData> + <items> + <StackString value="Check how DefineFunction2 handles flags involving arguments"/> + </items> + </PushData> + <Trace/> + <DeclareFunction2 name="foo" argc="0" regc="2" preloadArguments="1" suppressArguments="1" reserved="0"> + <actions> + <PushData> + <items> + <StackRegister reg="1"/> + <StackString value="arguments"/&...

...+ <String value="foo"/> + <String value="fscommand:quit"/> + <String value=""/> + </strings> + </Dictionary> + <DeclareFunction2 name="foo" argc="0" regc="0" preloadThis="0" suppressThis="0" preloadArguments="0" suppressArguments="0" preloadSuper="0" suppressSuper="0" preloadRoot="0" preloadParent="0" reserved="0" preloadGlobal="0"> +...

...<DoAction> + <actions> + <PushData> + <items> + <StackString value="Check how DefineFunction2 handles register counts"/> + </items> + </PushData> + <Trace/> + <DeclareFunction2 name="foo" argc="0" regc="0"> + <actions> + <PushData> + <items> + <StackString value="hi"/> + </items> + </PushData> + <StoreRegister reg="0"/> + <StoreRegister reg="1"/> +...