Displaying 6 results from an estimated 6 matches for "reg1071".
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2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
...0x391ac10: <multiple use>
0x391c8b0: v2f64 = scalar_to_vector 0x391ac10 srcLineNum= 10
0x3927b10: <multiple use>
0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0, 0x3927b10<0,2>
srcLineNum= 10
The code that gets produced looks like this:
%reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
[r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
%reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
[r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
%reg1073<def> = SHUFPDrri %reg1071, %reg1072...
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2008 Oct 02
6
[LLVMdev] Making Sense of ISel DAG Output
...> 0x391c8b0: v2f64 = scalar_to_vector 0x391ac10 srcLineNum= 10
> 0x3927b10: <multiple use>
> 0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0,
> 0x3927b10<0,2> srcLineNum= 10
>
> The code that gets produced looks like this:
>
> %reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
> %reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
> %reg1073<def> = SHUFPDrri...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
...v2f64 = scalar_to_vector 0x391ac10 srcLineNum= 10
>> 0x3927b10: <multiple use>
>> 0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0,
>> 0x3927b10<0,2> srcLineNum= 10
>>
>> The code that gets produced looks like this:
>>
>> %reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288,
>> Mem:LD(8,8)
>> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
>> %reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288,
>> Mem:LD(8,8)
>> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
>...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
..., 0x88c9540
SU(2): 0x88caab8: i32 = SLT 0x88c9dd8, 0x88caa50
SU(3): 0x88c9d80: ch = BNE 0x88caab8, 0x88cabd8, 0x88cacb8, 0x88c9dd8:1
Selected machine code:
bb49: 0x88c84c0, LLVM BB @0x88bee58, ID#14:
Predecessors according to CFG: 0x88c80b0 (#7) 0x88c8430 (#13)
%reg1070 = ADDiu %ZERO, 8193
%reg1071 = LW 0, <fi#6>
%reg1072 = SLT %reg1071, %reg1070
BNE %reg1072, %ZERO, mbb<bb20,0x88c8140>
Successors according to CFG: 0x88c8140 (#8) 0x88c8550 (#15)
Total amount of phi nodes to update: 0
Replacing.3 0x88cb4c8: i1 = setcc 0x88cb3f8, 0x88cb460, 0x88cb318
With: 0x88caab8: i1 = set...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...-1> is 4 bytes fixed at location [SP-68]
entry (0x8065970, LLVM BB @0x805fde8):
%reg1024 = load <fi#-1>
%reg1025 = load <fi#-2>
%reg1026 = load <fi#-3>
%reg1027 = load <fi#-4>
%reg1028 = move 1
setcc %reg1024, %reg1028
if v< goto %disp(label entry.selecttrue)
%reg1071 = move 0
goto %disp(label entry.selectcont)
entry.selecttrue (0x80659d0, LLVM BB @0x80639b0):
%reg1070 = move 1
entry.selectcont (0x8065a30, LLVM BB @0x80638b0):
%reg1030 = phi %reg1070, mbb<entry.selecttrue,0x80659d0>, %reg1071, mbb<entry,0x8065970>
%reg1029 = move %reg1030
shor...