search for: reg1031

...x8602d30): %reg1024 = OR4 %r3, %r3 %reg1025 = OR4 %r4, %r4 %reg1026 = LWZ 0, %reg1025 %reg1027 = LIS <ga:.str_1> %reg1028 = LIS <ga:.str_2> %reg1029 = LBZ 0, %reg1026 ADJCALLSTACKDOWN 56 %reg1030 = IMPLICIT_DEF_GPR %reg1031 = LA %reg1027, <ga:.str_1> %r3 = OR4 %reg1031, %reg1031 BL <ga:printf>, %r3 %reg1032 = OR4 %r3, %r3 <------------------- %reg1033 = EXTSB %reg1029 %reg1034 = LA %reg1028, <ga:.str_2> ADJCALLSTACKUP 56 ADJCALLSTACKDOWN...

...Joined. Result = R15,inf = [0,38:0)[110,118:2)[118,146:1) 0 at 0*-(38) 1 at 118-(146) 2 at 110-(118) 132 %R14<def> = MOVRdRr %reg1029<kill> Inspecting %reg1029,0.000000e+00 = [62,134:0) 0 at 62-(134) and R14,inf = [0,94:0)[134,146:1) 0 at 0*-(94) 1 at 134-(146): Interference! 76 %reg1031<def> = MOVRdRr %R1<kill> Inspecting R1,inf = [38,39:1)[54,78:0)[94,95:2) 0 at 54-(78) 1 at 38-(39) 2 at 94-(95) and %reg1031,0.000000e+00 = [78,86:1)[86,118:0) 0 at 86-(118) 1 at 78-(86): Interference! 108 %R15<def> = MOVRdRr %R0<kill> Can not coalesce physregs. 44 %reg...

On Thu, 29 Jun 2006, Fernando Magno Quintao Pereira wrote: > I am working in a register allocator for LLVM, and I realized that, > after I perform register allocation, there is many move instructions that > are dead code, and can safely be removed. It is easy for the RA algorithm > to remove these instructions. It seems to me that the only instructions > with dead definitions

Dear guys, I am working in a register allocator for LLVM, and I realized that, after I perform register allocation, there is many move instructions that are dead code, and can safely be removed. It is easy for the RA algorithm to remove these instructions. It seems to me that the only instructions with dead definitions that I should not remove are the calls. Is it true? I would like to know

...o even boundary. Since address register can't be AND-ed with anything, I move the value into general purpose register, to "and" and then move it into address register. Unfortunately, the register allocator crashes. Here's machine code: %reg1030 = - %reg1027, 1 %reg1031 = move %reg1030 %reg1032 = + %reg1031, -2 %reg1033 = move %reg1032 %ar1 = load64 %gr1<def>, %reg1033 and here's assertion: llc: LiveIntervals.cpp:507: void llvm::LiveIntervals::joinIntervals(): Assertion `rcA == rcB && "registers must be of the same...

...imp-def> %reg1096<def> = addC %reg1029<kill>, 0, %CCFLAGS<imp-def> %reg1097<def> = addC %reg1033<kill>, 0, %CCFLAGS<imp-def> %reg1098<def> = addC %reg1028<kill>, 0, %CCFLAGS<imp-def> %reg1099<def> = addC %reg1031<kill>, 0, %CCFLAGS<imp-def> %reg1100<def> = addC %reg1030, 0, %CCFLAGS<imp-def> %reg1101<def> = addC %reg1032<kill>, 0, %CCFLAGS<imp-def> %reg1102<def> = addC %reg1030<kill>, 0, %CCFLAGS<imp-def> br mbb<i...

...eg0 %reg1030<def> = MOVr %reg1027<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1037<def>, %reg1030<def> = LDR_POST %reg1030, %reg0, 4, pred:14, pred:%reg0 %reg1029<def> = ADDrr %reg1037<kill>, %reg1028, pred:14, pred:%reg0, opt:%reg0 %reg1031<def> = SUBri %reg1026<kill>, 1, pred:14, pred:%reg0, opt:%reg0 CMPzri %reg1031, 0, pred:14, pred:%reg0, %CPSR<imp-def> %reg1038<def> = MOVr %reg1031<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1039<def> = MOVr %reg1030<kill>, pred:14,...

...%reg1096<def> = addC %reg1029<kill>, 0, %CCFLAGS<imp-def> > %reg1097<def> = addC %reg1033<kill>, 0, %CCFLAGS<imp-def> > %reg1098<def> = addC %reg1028<kill>, 0, %CCFLAGS<imp-def> > %reg1099<def> = addC %reg1031<kill>, 0, %CCFLAGS<imp-def> > %reg1100<def> = addC %reg1030, 0, %CCFLAGS<imp-def> > %reg1101<def> = addC %reg1032<kill>, 0, %CCFLAGS<imp-def> > %reg1102<def> = addC %reg1030<kill>, 0, %CCFLAGS<imp-def> >...

...eters for a call: %reg1028<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0 %reg1029<def> = MOV32rm <fi#2>, 1, %reg0, 4, %reg0 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %reg1030<def> = LEA64r %RIP, 1, %reg0, <ga:@.str> %reg1031<def> = MOV8r0 %EFLAGS<imp-def,dead> %RDI<def> = MOV64rr %reg1030 %ESI<def> = MOV32rr %reg1028 %EDX<def> = MOV32rr %reg1029 %AL<def> = MOV8rr %reg1031 CALL64pcrel32 <ga:@printf>, %RDI, %ESI, %EDX, %AL, %RAX<imp-def>, %RDX<imp-def>, %RSI<i...

...%reg1028 = ADD32rr %reg1026, %reg1027 %reg1029 = IMUL32rr %reg1028, %reg1027 MOV32mr %ESP, 1, %NOREG, 4, %reg1029 MOV32mi %ESP, 1, %NOREG, 0, <ga:.str_1> CALLpcrel32 <ga:printf> ADJCALLSTACKUP 8, 0 %reg1030 = MOV32rr %EAX %reg1031 = IMPLICIT_DEF_GR32 %EAX = MOV32rr %reg1031 RET My allocator produces this mapping: FNSTCW16m := MOV8mi := FLDCW16m := MOV32rm EAX := MOV32rm EAX := EAX MOVSX32rm8 ECX := EAX MOVSX32rm8 EAX := EAX...

...Final schedule *** SU(0): 0x88c8eb0: ch = EntryToken SU(1): 0x88c8f08: i32 = ADDiu 0x88c8bf0, 0x88c90f8 SU(2): 0x88c9298: ch = SW 0x88c8f08, 0x88c8800, 0x88c8c88, 0x88c8eb0 Selected machine code: cond_false: 0x88c7db8, LLVM BB @0x88be190, ID#2: Predecessors according to CFG: 0x88c7918 (#0) %reg1031 = ADDiu %ZERO, 17000 SW %reg1031, 0, <fi#3> Successors according to CFG: 0x88c7e48 (#3) Total amount of phi nodes to update: 0 Lowered selection DAG: SelectionDAG has 11 nodes: 0x88c8bf0: ch = EntryToken 0x88c87e0: i32 = FrameIndex <3> 0x88c90f8: <multiple use>...

On Wed, 2010-04-14 at 17:30 -0700, Hisham Chowdhury wrote: > > > > - Is there a utility to clone a MachineBasicBlock in LLVM > > > > > > There is CloneBasicBlock routine in ./lib/Transforms/Utils/CloneFunction.cpp - Sanjiv > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu

...ntry.selecttrue (0x80659d0, LLVM BB @0x80639b0): %reg1070 = move 1 entry.selectcont (0x8065a30, LLVM BB @0x80638b0): %reg1030 = phi %reg1070, mbb<entry.selecttrue,0x80659d0>, %reg1071, mbb<entry,0x8065970> %reg1029 = move %reg1030 shortcirc_next.0 (0x8065a90, LLVM BB @0x805ffc8): %reg1031 = move 1 setcc %reg1026, %reg1031 if v< goto %disp(label shortcirc_next.0.selecttrue) %reg1073 = move 0 goto %disp(label shortcirc_next.0.selectcont) shortcirc_next.0.selecttrue (0x8065af0, LLVM BB @0x8063bb0): %reg1072 = move 1 shortcirc_next.0.selectcont (0x8065b50, LLVM BB @0x8063b08):...

...// each %reg is a sub-register // r1, r2, r3, r4 here are virtual register number mul %reg1024, r1, r2 // x mul %reg1025, r1, r2 // y mul %reg1026, r1, r2 // z add %reg1027, r3, r4 // w sub %reg1028, %reg1024, r1 sub %reg1029, %reg1025, r1 sub %reg1030, %reg1026, r1 sub %reg1031, %reg1027, r1 So I decided to model each 4-element register as one Register in *.td file. Here are the details. Since all the 4 elements of a vector register occupy the same 'alloca', during the conversion of shader assembly to LLVM IR, I check if a vector register is written (to differe...

  Hello, I am trying to clone a machine basic block when I ran into some issues, where I am not able to make some headway. Any of yours help is highly appreciated here: My question is about Machine Basic Block Duplication:   -          Is there a utility to clone a MachineBasicBlock in LLVM? I found utility to clone machineInstrs, but couldn’t find similar utility for MachineBasicBlock. So, I

...1096<def> = addC %reg1029<kill>, 0, %CCFLAGS<imp-def> >> %reg1097<def> = addC %reg1033<kill>, 0, %CCFLAGS<imp-def> >> %reg1098<def> = addC %reg1028<kill>, 0, %CCFLAGS<imp-def> >> %reg1099<def> = addC %reg1031<kill>, 0, %CCFLAGS<imp-def> >> %reg1100<def> = addC %reg1030, 0, %CCFLAGS<imp-def> >> %reg1101<def> = addC %reg1032<kill>, 0, %CCFLAGS<imp-def> >> %reg1102<def> = addC %reg1030<kill>, 0, %CCFLAGS<imp-def...

...4 here are virtual register number > > mul %reg1024, r1, r2 // x > mul %reg1025, r1, r2 // y > mul %reg1026, r1, r2 // z > > add %reg1027, r3, r4 // w > > sub %reg1028, %reg1024, r1 > sub %reg1029, %reg1025, r1 > sub %reg1030, %reg1026, r1 > sub %reg1031, %reg1027, r1 > > So I decided to model each 4-element register as one Register in > *.td file. > > Here are the details. > > Since all the 4 elements of a vector register occupy the same > 'alloca', > during the conversion of shader assembly to LLVM IR, I che...

On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer code, but since LLVM is so nearer to the optimal code sequence i wanted to reach it. In LLVM, copies are