search for: r28

Andrew Lenharth wrote: > On Tue, 2006-05-23 at 13:04 -0500, Chris Lattner wrote: >> > That approach sounds suboptimal. By "reserving" one register we can >> > already cause some values to be spilled, that otherwise would be stored >> > in register. >> >> Right. >> >> PowerPC has the same problem in certain cases. For example,

On Tue, 2006-05-23 at 13:04 -0500, Chris Lattner wrote: > > That approach sounds suboptimal. By "reserving" one register we can already > > cause some values to be spilled, that otherwise would be stored in > > register. > > Right. > > PowerPC has the same problem in certain cases. For example, vector loads > only support reg+reg addressing, which

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

...warfRegNum<[23]>; def R24 : DLXR<24, "r24">, DwarfRegNum<[24]>; def R25 : DLXR<25, "r25">, DwarfRegNum<[25]>; def R26 : DLXR<26, "r26">, DwarfRegNum<[26]>; def R27 : DLXR<27, "r27">, DwarfRegNum<[27]>; def R28 : DLXR<28, "r28">, DwarfRegNum<[28]>; def R29 : DLXR<29, "r29">, DwarfRegNum<[29]>; def R30 : DLXR<30, "r30">, DwarfRegNum<[30]>; def R31 : DLXR<31, "r31">, DwarfRegNum<[31]>; // Register classes def DLXRegs :...

...0x00000026 r12: 0x8fe71ac7 r13: 0x00000000 r14: 0x000021bc r15: 0x00000000 r16: 0xbffffcb4 r17: 0x00000001 r18: 0x00000000 r19: 0x000016d4 r20: 0x00000000 r21: 0x00000000 r22: 0x00000000 r23: 0x00000000 r24: 0x8fe4b3d8 r25: 0x00000002 r26: 0x00000002 r27: 0x00000000 r28: 0x00001610 r29: 0x00000000 r30: 0x8fe484d8 r31: 0x8fe09ecc

...code 1 Stop in /usr/ports/mail/dovecot/work/dovecot-1.0.rc28. *** Error code 1 Stop in /usr/ports/mail/dovecot. *** Error code 1 Stop in /usr/ports/mail/dovecot. ** Command failed [exit code 1]: /usr/bin/script -qa /tmp/portupgrade.29635.0 env UPGRADE_TOOL=portupgrade UPGRADE_PORT=dovecot-1.0.r28 UPGRADE_PORT_VER=1.0.r28 make ** Fix the problem and try again. ** Listing the failed packages (*:skipped / !:failed) ! mail/dovecot (dovecot-1.0.r28) (linker error) ---> Packages processed: 0 done, 0 ignored, 0 skipped and 1 failed -- ? ?????????, ?????? ????? ??? "?????...

...led to idle channel 0xcccc0000 [X[361]] mars 20 20:49:18 titan kernel: nouveau E[plugin-containe[2417]] failed to idle channel 0xcccc0000 [plugin-containe[2417]] mars 20 20:49:33 titan kernel: nouveau E[plugin-containe[2417]] failed to idle channel 0xcccc0000 [plugin-containe[2417]] linux 3.14.rc7.r28 (commit ea1cd65) mesa 10.1.0-4 nouveau-dri 10.1.0-4 $ glxinfo | grep Open OpenGL vendor string: nouveau OpenGL renderer string: Gallium 0.4 on NVE4 OpenGL core profile version string: 3.3 (Core Profile) Mesa 10.1.0 OpenGL core profile shading language version string: 3.30 OpenGL core profile conte...

...code in my backend, but unless I do the following, the registers are never considered 'live' into the call. / Handle a function call let isCall = 1, Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87,...

...?) def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]> { } 3) If not, does this means I have to write the whole LLVM backend based on the basic llvm::TargetMachine & llvm::TargetData, just like what CBackend does? -------------------------------------------------------- Wei H...

Hi Micah, > In X86InstrInfo.td for Call Instructions, it mentions that Uses for > argument registers are added manually. Can someone point me to the > location where they are added as the comment doesn't reference a > where or how? the register uses are added by the function X86TargetLowering::LowerCall() during the DAG Lowering phase. This is the relevant code segment: // Add

...ineFunctionPass.cpp:33 For the purpose of this question, you can assume HexagonMachineScheduler.cpp == MachineScheduler.cpp and VLIWMachineScheduler == ScheduleDAGMI The instruction being moved is a simple call: let isCall = 1, neverHasSideEffects = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1, USR] in { def CALLv3 : JInst<(outs), (ins calltarget:$dst), "call $dst", []>, Requires<[HasV3T]>; } CALLv3 <ga:@printf>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %R31&lt...

...[XXX], 32, [R0, R1, R2, R3,   > > R4, R5, R6, R7, R8, R9, > >                                                    R10, R11, R12,   > > R13, R14, R15, R16, R17, R18, R19, > >                                                    R20, R21, R22,   > > R23, R24, R25, R26, R27, R28, R29, > >                                                    R30, R31]> { > > } > > > 3) If not, does this means I have to write the whole LLVM backend   > > based on the basic llvm::TargetMachine & llvm::TargetData, just like   > > what CBackend does? > &...

...s<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > R4, R5, R6, R7, R8, R9, > R10, R11, R12, > R13, R14, R15, R16, R17, R18, R19, > R20, R21, R22, > R23, R24, R25, R26, R27, R28, R29, > R30, R31]> { > } > > 3) If not, does this means I have to write the whole LLVM backend > based on the basic llvm::TargetMachine & llvm::TargetData, just like > what CBackend does? > > > ----------------...

...clob1] = r23, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r24, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r25, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r26, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r27, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r28, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r29, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r30, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r31, 16; \ + ;; \ + mov clob1 = ar.unat; \ + movl clob0 = XSI_B1NAT; \ + ;; \ + st8 [clob0] = clob1; \ + mov ar.unat =...

...+ fstd,ma %fr14,8(%r19) + fstd,ma %fr15,8(%r19) + fstd,ma %fr16,8(%r19) + fstd,ma %fr17,8(%r19) + fstd,ma %fr18,8(%r19) + fstd,ma %fr19,8(%r19) + fstd,ma %fr20,8(%r19) + fstd %fr21,0(%r19) + bv %r0(%rp) + copy %r0,%r28 + .procend + + .text + .align 4 + .global longjmp + .export longjmp, code + .proc + .callinfo +longjmp: + ldw 0(%r26),%r3 + ldw 8(%r26),%r4 + ldw 12(%r26),%r5 + ldw 16(%r26),%r6 + ldw 20(%r26),%r7 + ldw 24(%r26),%r8 + ldw...

...r11: 0xa0004374 r12: 0x90004fa0 r13: 0x00000000 r14: 0x9001b340 r15: 0x00030860 r16: 0x00000001 r17: 0x0003ccd0 r18: 0x9001b340 r19: 0x0003ccd0 r20: 0x000385a4 r21: 0x00977f60 r22: 0x00977f60 r23: 0x9001b340 r24: 0x0003ccd0 r25: 0x00000004 r26: 0x0003ccd4 r27: 0xffffffff r28: 0x0003ccd0 r29: 0x0003ccd0 r30: 0x0003ccd4 r31: 0x9000b750 ********** Date/Time: 2003-04-01 21:39:19 -0500 OS Version: 10.2.4 (Build 6I32) Host: Albus.local. Command: rsync PID: 2350 Exception: EXC_BAD_ACCESS (0x0001) Codes: KERN_INVALID_ADDRESS (0x0001) at 0xbff7fee0...

...004001 >(XEN) r17 : f000000004105214 r18 : 0000000000001ba9 r19 : f000000004105210 >(XEN) r20 : a00000010095be10 r21 : 0000000000000000 r22 : 0000000000000001 >(XEN) r23 : 0000000000000000 r24 : f0000000041c7e20 r25 : f0000000041c7e28 >(XEN) r26 : 0000000000000000 r27 : 0000000000000000 r28 : 000000000000001d >(XEN) r29 : 0000000000000000 r30 : 0000000000000000 r31 : f000000004114098 >(XEN) >(XEN) Call Trace: >(XEN) [<f000000004094820>] show_stack+0x80/0xa0 >(XEN) sp=f0000000041c7500 >bsp=f0000000041c1018 >(XEN) [<f00000...