llvm dev - May 2006 - [LLVMdev] Re: Spilling register and frame indices

On Tue, 2006-05-23 at 13:04 -0500, Chris Lattner wrote:
> > That approach sounds suboptimal. By "reserving" one register
we can already
> > cause some values to be spilled, that otherwise would be stored in
> > register.
> 
> Right.
> 
> PowerPC has the same problem in certain cases.  For example, vector loads 
> only support reg+reg addressing, which means you have to load the offset 
> from the stack pointer into a register before doing the load.
> 
> In the case of PPC, we currently just reserve a register for this purpose. 
> This is suboptimal, but doesn't cause a significant performance issue 
> normally.
Alpha also has this problem for some offsets.  I haven't looked at what
PPC does, but alpha has the loads and stores that might need the
indexing kill an extra register, thus ensuring it is available for the
inserted instruction.  You don't need to reserve a register (globally)
only for these cases, just make sure you have it available when you need
it.

Andrew

Andrew Lenharth wrote:
> On Tue, 2006-05-23 at 13:04 -0500, Chris Lattner wrote:
>> > That approach sounds suboptimal. By "reserving" one
register we can
>> > already cause some values to be spilled, that otherwise would be
stored
>> > in register.
>> 
>> Right.
>> 
>> PowerPC has the same problem in certain cases.  For example, vector
loads
>> only support reg+reg addressing, which means you have to load the
offset
>> from the stack pointer into a register before doing the load.
>> 
>> In the case of PPC, we currently just reserve a register for this
>> purpose. This is suboptimal, but doesn't cause a significant
performance
>> issue normally.
> 
> Alpha also has this problem for some offsets.  I haven't looked at what
> PPC does, but alpha has the loads and stores that might need the
> indexing kill an extra register, thus ensuring it is available for the
> inserted instruction.  You don't need to reserve a register (globally)
> only for these cases, just make sure you have it available when you need
> it.
I'm sorry I don't understand your suggestion. Unless I reserve a
register
globally, I might not have any register at all to use for addressing.

- Volodya

On Wed, 2006-05-24 at 10:07 +0400, Vladimir Prus wrote:
> Andrew Lenharth wrote: 
> > Alpha also has this problem for some offsets.  I haven't looked at
what
> > PPC does, but alpha has the loads and stores that might need the
> > indexing kill an extra register, thus ensuring it is available for the
> > inserted instruction.  You don't need to reserve a register
(globally)
> > only for these cases, just make sure you have it available when you
need
> > it.
> 
> I'm sorry I don't understand your suggestion. Unless I reserve a
register
> globally, I might not have any register at all to use for addressing.
> - Volodya
If you look in AlphaInstrFormats.td the MForm class reserves R28 for
index calculations.  It does this by adding it to the Defs set for those
instructions.  Thus since the instruction is set as killing R28, it is
available for use if I insert an instruction immediately before the
ld/st.  Thus R28 can be used by the register allocator, but the RA makes
sure it is unused when there is an ld/st, thus giving me a scratch
register to use for index calculations with out completely reserving
R28.

Andrew