search for: printmemoperand

I'm trying to write a store pattern that accepts both i32 and f32, however, when tablegen generates the code, it only generates the code for i32 only. def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; def MEM : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR, GPR); } def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def global_store : PatFrag<(ops node:$val, node:$ptr), (st node:$val, node:$ptr), [{ return isGlob...

...e a store pattern that accepts both i32 and f32, > however, when tablegen generates the code, it only generates the > code for i32 only. > > def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; > def MEM : Operand<i32> { > let PrintMethod = "printMemOperand"; > let MIOperandInfo = (ops GPR, GPR); > } > def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore, > [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; > > def global_store : PatFrag<(ops node:$val, node:$ptr), > (st node:$val, node:$ptr), [...

...lass(MVT::iPTR, .. )) 3) I added method addPointerRegClass() to my InstrInfo class The compiler generates the some code as before, but that seems to be ok, because I haven't used ptr_rc yet. 4) I changed the address mode MEMri: def MEMri : Operand<iPTR> { let PrintMethod = "printMemOperand"; // was: let MIOperandInfo = (ops IntRegs, i32imm); let MIOperandInfo = (ops ptr_rc, i32imm); } for the C code int c; void f(void) { c = 4711; } I get the error message: Register class of operand and regclass of use don't agree! Operand = 0 Op->Val = 0x42b08d60: i32 = SETHIi...

...XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPRegs, GPRegs); let EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram $dst,$src",...

...re: // This class provides load/store address format selection support // class Addr< int numArgs, string funcName, dag opInfo > : Operand<i64>, ComplexPattern< i64, numArgs, funcName, [], [SDNPWantParent] > { let MIOperandInfo = opInfo; } let PrintMethod = "printMemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; def ADDR_SHLI : Addr< 2, "SelectAddr...

...d $dst,$addr", [(set CPURegs:$dst, (load ADDRrli:$addr))]>; Where ADDRrli and MEMrli are: def ADDRrli : ComplexPattern<i32, 2, "SelectADDRrli", [frameindex], []>; // Register + long immediate. def MEMrli : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops CPURegs, limm32); } Does anyone have any suggestions on how to debug this issue, or what information a target must be giving to allow live interval analysis to work ok? (Possibly register clobbering information or the like?) Thanks, Stephen -------------- next p...

Hello > Finally, I don't know how to describe following instructions in > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files > should I use to finish this description? Do you need the isel support for them? If yes, then you should custom isel them. iirc ARM and SystemZ backends have similar instructions, while only the first one supports full isel for them. In

Hmm, I'm getting nowhere pretty fast. It seems 68000 with its CISC nature is quite complex to implement for a novice. I can see how to implement simple stuff, like -- move dn, dn move dn, (an) As that just turns into stores, sets, etc. But how would you represent things like indexed access? move dn, (an,dn) move dn, offset(an) Can I only really define very simple operations for the main

...MemEncoding: test/MC/Mips/loongson3a/valid.s:32:30: error: expected memory with 32-bit signed offset         gslbx           $2,0($3,$4)                                       ^ I just copy-n-paste  mem_generic  and  getMemEncoding: def gs_mem : Operand<iPTR> {   let PrintMethod = "printMemOperand";   let MIOperandInfo = (ops ptr_rc, ptr_rc, simm16); ^-- for two registers   let EncoderMethod = "getGSMemEncoding";                                             ^-- just encoding two registers and one offset   let ParserMatchClass = MipsMemAsmOperand;   let OperandType = &qu...

i'm getting a Could not infer all types in pattern! error in my backend. it is happening on the following instruction: VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32} VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)). how do i make it use appropriate types? in other words if it is f32 then use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start? any help is appreciated.

...thod addPointerRegClass() to my InstrInfo class > > The compiler generates the some code as before, but that seems to > be ok, because I haven't used ptr_rc yet. > > 4) I changed the address mode MEMri: > > def MEMri : Operand<iPTR> { > let PrintMethod = "printMemOperand"; > // was: let MIOperandInfo = (ops IntRegs, i32imm); > let MIOperandInfo = (ops ptr_rc, i32imm); > } > > for the C code int c; void f(void) { c = 4711; } I get the error > message: > > Register class of operand and regclass of use don't agree! > Operand =...

Hi, all: Now I'm working on writing a backend for Moto MCore, but I don't know how to describe some instructions. First, I've already written MCoreRegisterInfo.td like these: class MCoreReg<bits<4> num, string name> : Register<name> { let Namespace = "MCore"; field bits<4> Num = num; } def R0 : MCoreReg< 0, "R0">,