search for: pfifo

...ffffff816ffae9>] system_call_fastpath+0x16/0x1b [ 402.178347] Code: 66 0f 1f 84 00 00 00 00 00 55 48 c7 c6 2a 0b a5 81 48 89 e5 e8 f0 fe ff ff b8 ff ff ff ff 5d c3 66 0f 1f 84 00 00 00 00 00 8b 07 <c3> 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 48 81 fe ff ff 03 00 [ 406.548852] nouveau W[ PFIFO][0000:00:05.0] unknown intr 0x00200000, ch 3 [ 410.926503] nouveau W[ PFIFO][0000:00:05.0] unknown intr 0x00200000, ch 3 [ 415.281709] nouveau W[ PFIFO][0000:00:05.0] unknown intr 0x00200000, ch 3 [ 419.627002] nouveau W[ PFIFO][0000:00:05.0] unknown intr 0x00200000, ch 3 [ 424.066039] no...

Hi to all, i''m following this guide (http://www.opalsoft.net/qos/DS-28.htm), is very detailed, but i''m a bit confused about queuing disciplinse of leaf classes. In this guide the author uses PFIFO (see the scheme that i attached at message) in this way: # tc class add dev eth0 parent 1:21 handle 210: pfifo lmit 10 # tc class add dev eth0 parent 1:22 handle 220: pfifo lmit 10 # tc class add dev eth0 parent 1:23 handle 230: pfifo lmit 10 # tc class add dev eth0 parent 1:24 handle 240: pfifo l...

...llocated 1280x1024 fb: 0x60000, bo ffff88007cfad000 [ 0.471980] fbcon: nouveaufb (fb0) is primary device A snippets of the logs while failing (taken from rsyslog): 06-07-2013 17:15 .err ::: nouveau E[ DRM] GPU lockup - switching to software fbcon 06-07-2013 17:15 .warning ::: nouveau W[ PFIFO][0000:01:00.0] INTR 0x00000100: 0x0000000a 06-07-2013 17:15 .warning ::: nouveau W[ PFIFO][0000:01:00.0] INTR 0x00000100: 0x0000000a 06-07-2013 17:15 .warning ::: nouveau W[ PFIFO][0000:01:00.0] INTR 0x00000100: 0x0000000a 06-07-2013 17:15 .warning ::: nouveau W[ PFIFO][0000:01:00.0] INTR 0x0...

...2, with both the stock kernel and 3.19.0-22, nouveau fills kern.log with messages like these: ====================8< CUT HERE 8<================================================================= $ tail -n 3000 kern.log.1 | head -n 50 Jul 10 18:02:35 dioo-XPS kernel: [114893.357149] nouveau E[ PFIFO][0000:01:00.0] PBDMA0: ch 2 [Xorg[16558]] subc 5 mthd 0x0000 data 0x0000906e Jul 10 18:02:35 dioo-XPS kernel: [114893.406261] nouveau E[ PFIFO][0000:01:00.0] PBDMA0: LBREQ Jul 10 18:02:35 dioo-XPS kernel: [114893.406269] nouveau E[ PFIFO][0000:01:00.0] PBDMA0: ch 2 [Xorg[16558]] subc 5 mthd 0x0000...

...0000 data 0x00000000 0x00011000 [ 73.743052] nouveau [ DRM] 1 available performance level(s) [ 73.822016] nouveau [ DRM] 3: core 567MHz shader 1400MHz memory 500MHz fanspeed 100% [ 73.929532] nouveau [ DRM] c: core 566MHz shader 1400MHz memory 499MHz [ 74.052172] nouveau E[ PFIFO][0001:01:00.0] DMA_PUSHER - ch 1 [DRM] get 0x0000000000 put 0x0000000000 ib_get 0x00000000 ib_put 0x00000001 state 0xa0000000 (err: IB_EMPTY) push 0x00406040 [ 74.293113] nouveau [ DRM] MM: using M2MF for buffer copies [ 74.409001] nouveau [ DRM] allocated 1280x1024 fb: 0x70000, bo ff...

...6 deletions(-) diff --git a/docs/hw/fifo/intro.rst b/docs/hw/fifo/intro.rst index 8b1d69d..0e023bf 100644 --- a/docs/hw/fifo/intro.rst +++ b/docs/hw/fifo/intro.rst @@ -10,7 +10,7 @@ FIFO overview Introduction ============ -Commands to most of the engines are sent through a special engine caled PFIFO. +Commands to most of the engines are sent through a special engine called PFIFO. PFIFO maintains multiple fully independent command queues, known as "channels" or "FIFO"s. Each channel is controlled through a "channel control area", which is a region of MMIO [pre-N...

...670MX] (rev a1) Operating system: Archlinux with linux 3.19.3-3-ARCH nouveau-fw is installed and nouveau.config=NvGrUseFW=1 is in the kernel parameters. I logged in via SSH into the blocked machine and dumped dmesg's output, it produced a 6MiB sized file of only: [ 432.267634] nouveau E[ PFIFO][0000:01:00.0] PBDMA0: ch 6 [gstglcontext[1984]] subc 0 mthd 0x000c data 0x2001054e [ 432.267645] nouveau E[ PFIFO][0000:01:00.0] PBDMA0: METHOD [ 432.267647] nouveau E[ PFIFO][0000:01:00.0] PBDMA0: ch 6 [gstglcontext[1984]] subc 0 mthd 0x000c data 0x2001054e [ 432.267658] nouveau E[ PFIFO...

Resend of patch #7 to fix behaviour when failing to pause parts of the GPU

I''m trying to configure 4 queues with strict priorities based on DSCP. I tried to following commands, but it seems that the filters I defined have no effect tc qdisc add dev eth0 root handle 1: prio bands 4 tc qdisc add dev eth0 parent 1:0 handle 10: pfifo limit 100 tc qdisc add dev eth0 parent 1:1 handle 20: pfifo limit 100 tc qdisc add dev eth0 parent 1:2 handle 30: pfifo limit 100 tc qdisc add dev eth0 parent 1:3 handle 40: pfifo limit 100 tc filter add dev eth0 parent 1:0 protocol ip prio 1 u32 match ip tos 224 0xff flowid 10: tc filter add dev e...

Hello ppl, I''m playing with the pfifo scheduler, its simple, and i cannot understand what''s wrong. So, i have test machine, with one interface eth0, and i want to send no more than 3 packets/sec out of that interface, so i do: tc qdisc add dev eth0 root pfifo limit 3 And i get pfifo scheduler on eth0 with limit of 3, but it...

...d OS: Linux (All) Reporter: adham3322 at gmail.com Hardware: x86-64 (AMD64) Status: NEW Version: unspecified Component: Driver/nouveau Product: xorg get this error after installing 3.12 using elementary os nouveau W[ PFIFO][0000:01:00.0] INTR 0x00000100: 0x00000011? -- You are receiving this mail because: You are the assignee for the bug. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/nouveau/attachments/20131124/9724a09a/attachment.html>

...s: NEW Version: unspecified Component: Drivers/DRI/nouveau Product: Mesa This is a regression from 3.12 to 3.13 (still present on nouveau master). I started seeing these in dmesg: [ 64.358170] hda-codec: out of range cmd 0:6:707:fffffffc [ 2310.511292] nouveau W[ PFIFO][0000:01:00.0] INTR 0x01000000: 0x00000005 [ 2310.778618] nouveau W[ PFIFO][0000:01:00.0] INTR 0x01000000: 0x00000005 [ 2310.837097] nouveau W[ PFIFO][0000:01:00.0] INTR 0x01000000: 0x00000005 [ 2310.895963] nouveau W[ PFIFO][0000:01:00.0] INTR 0x01000000: 0x00000005 [ 2311.231493] nouveau W[...

...--- diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c index 85a0e78..4f46d8b 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fence.c +++ b/drivers/gpu/drm/nouveau/nvc0_fence.c @@ -161,11 +161,12 @@ nvc0_fence_suspend(struct nouveau_drm *drm) struct nouveau_fifo *pfifo = nouveau_fifo(drm->device); struct nvc0_fence_priv *priv = drm->fence; int i; + u32 chan = pfifo->max + 1; - priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32)); + priv->suspend = vmalloc(chan * sizeof(u32)); if (priv->suspend) { - for (i = 0; i <= pfifo->max...

...x.org Created attachment 115843 --> https://bugs.freedesktop.org/attachment.cgi?id=115843&action=edit dmesg output Since installing Plasma 5, I'm getting a lot of lockups even with compositing disabled. As far as I can tell, the relevant part of dmesg is [ 2043.225653] nouveau E[ PFIFO][0000:08:00.0] read fault at 0x0000490000 [PTE] from GR/S\ CC on channel 0x007edf8000 [kwin_x11[2256]] [ 2043.225660] nouveau E[ PFIFO][0000:08:00.0] PGR engine fault on channel 12, recovering\ ... [ 2092.200410] nouveau E[ PFIFO][0000:08:00.0] PBDMA1: SIGNATURE [ 2092.200416] nouveau E[ PFIF...

...e <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/timer.h> @@ -293,6 +294,41 @@ calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) return ret; } +int +nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(clk); + + /* halt and idle execution engines */ + nv_mask(clk, 0x020060, 0x00070000, 0x00000000); + nv_mask(clk, 0x002504, 0x00000001, 0x00000001); + /* Wait until the interrupt handler is finished */ + if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) + return -EBUSY; + + if (pf...

Re-resend of patch #7 to move the _post and _pre function prototypes to nva3.h

...e <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/timer.h> @@ -293,6 +294,41 @@ calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) return ret; } +int +nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) +{ + struct nouveau_fifo *pfifo = nouveau_fifo(clk); + + /* halt and idle execution engines */ + nv_mask(clk, 0x020060, 0x00070000, 0x00000000); + nv_mask(clk, 0x002504, 0x00000001, 0x00000001); + /* Wait until the interrupt handler is finished */ + if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) + return -EBUSY; + + if (pf...

...onbons67 at internet.lu QAContact: xorg-team at lists.x.org Created an attachment (id=33272) --> (http://bugs.freedesktop.org/attachment.cgi?id=33272) Kernel log for both scenarios (debug messages not captured) Nouveau fails to fully resume from suspend to ram complaining with "PFIFO still angry after 101 spins" and monitor just shows garbage (advertised fallback software fbcon seems not to work). All is done with KMS on linux console, without running X. 02:00.0 VGA compatible controller [0300]: nVidia Corporation NVCrush11 [GeForce2 MX Integrated Graphics] [10de:...

Hi all, First, let me say I''ve been most impressed with how quickly and professionally people on this list ask and answer questions. Next, let me say that with which I need help is properly configuring strict PQ, and gathering certain stats. Specifically: - I need to create a priority queue with four queues (let''s say they are of high, medium, normal, and low priority) - I

...Assignee: nouveau at lists.freedesktop.org Reporter: xenith at overtmind.com QA Contact: xorg-team at lists.x.org Created attachment 119489 --> https://bugs.freedesktop.org/attachment.cgi?id=119489&action=edit EVGA GTX-660SC vbios.rom [52879.546431] nouveau E[ PFIFO][0000:01:00.0] read fault at 0x0002974000 [PTE] from GR/GPC1/T1_0 on channel 0x023f741000 [Xorg[1978]] [52879.546435] nouveau E[ PFIFO][0000:01:00.0] PGRAPH engine fault on channel 7, recovering... [52879.546445] nouveau E[ PGRAPH][0000:01:00.0] TRAP ch 7 [0x023f741000 Xorg[1978]] [52879.546451]...